blob: 0879ba29a5feb5669e82f306a15dbdf087f2f3a2 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/sbefw/app/power/sbecmdgeneric.C $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
/*
* @file: ppe/sbe/sbefw/sbecmdgeneric.C
*
* @brief This file contains the SBE generic Commands
*
*/
#include "sbecmdgeneric.H"
#include "sbefifo.H"
#include "sbetrace.H"
#include "sbe_sp_intf.H"
#include "sbe_build_info.H"
#include "sbeFifoMsgUtils.H"
#include "sbeFFDC.H"
#include "sberegaccess.H"
#include "sbestates.H"
#include "sbeHostMsg.H"
#include "sbeHostUtils.H"
#include "sbeglobals.H"
#include "sbeXipUtils.H"
#include "fapi2.H"
//#include "p9_xip_image.h"
using namespace fapi2;
#ifdef __SBEFW_SEEPROM__
void updatePsuCapabilities(uint32_t * capability)
{
capability[PSU_CORE_CONTROL_CAPABILITY_START_IDX] =
PSU_CONTROL_DEADMAN_LOOP;
capability[PSU_CORE_CONTROL_CAPABILITY_START_IDX+1] =
PSU_RESERVED_1;
capability[PSU_SCOM_CAPABILITY_START_IDX] =
PSU_DEFAULT_CAPABILITY_D2;
capability[PSU_SCOM_CAPABILITY_START_IDX+1] =
PSU_RESERVED_2;
capability[PSU_RING_CAPABILITY_START_IDX] =
PSU_PUT_RING_FROM_IMAGE_SUPPORTED;
capability[PSU_RING_CAPABILITY_START_IDX+1] =
PSU_RESERVED_3;
capability[PSU_TIMER_CAPABILITY_START_IDX] =
PSU_CONTROL_TIMER_SUPPORTED;
capability[PSU_TIMER_CAPABILITY_START_IDX+1] =
PSU_RESERVED_4;
capability[PSU_MPIPL_CAPABILITY_START_IDX] =
PSU_DEFAULT_CAPABILITY_D5;
capability[PSU_MPIPL_CAPABILITY_START_IDX+1] =
PSU_RESERVED_5;
capability[PSU_SECURITY_CONTROL_CAPABILITY_START_IDX] =
PSU_UNSECURE_MEM_REGION_SUPPORTED;
capability[PSU_SECURITY_CONTROL_CAPABILITY_START_IDX+1] =
PSU_RESERVED_6;
capability[PSU_GENERIC_CHIPOP_CAPABILITY_START_IDX] =
PSU_GET_SBE_CAPABILITIES_SUPPPORTED |
PSU_READ_SBE_SEEPROM_SUPPORTED |
PSU_SET_FFDC_ADDRESS_SUPPORTED |
PSU_QUISCE_SUPPORTED |
PSU_SET_SYSTEM_FABRIC_ID_MAP_SUPPORTED |
PSU_STASH_MPIPL_CONFIG_SUPPORTED;
capability[PSU_GENERIC_CHIPOP_CAPABILITY_START_IDX+1] =
PSU_RESERVED_7;
}
void updateFifoCapabilities(uint32_t * capability)
{
// @TODO via RTC : 160602
// Update Capability flags based on lastes spec.
capability[IPL_CAPABILITY_START_IDX] =
EXECUTE_ISTEP_SUPPPORTED |
SUSPEND_IO_SUPPPORTED |
FLUSH_NVDIMM_SUPPPORTED;
capability[IPL_CAPABILITY_START_IDX+1] =
RESERVED_A1_CAPABILITIES;
capability[SCOM_CAPABILITY_START_IDX] =
GET_SCOM_SUPPPORTED |
PUT_SCOM_SUPPPORTED |
MODIFY_SCOM_SUPPPORTED |
PUT_SCOM_UNDER_MASK_SUPPPORTED ;
capability[SCOM_CAPABILITY_START_IDX+1] =
RESERVED_A2_CAPABILITIES;
capability[RING_CAPABILITY_START_IDX] =
GET_RING_SUPPPORTED |
PUT_RING_SUPPPORTED |
PUT_RING_FROM_IMAGE_SUPPPORTED;
capability[RING_CAPABILITY_START_IDX+1] =
RESERVED_A3_CAPABILITIES;
capability[MEMORY_CAPABILITY_START_IDX] =
GET_MEMORY_SUPPPORTED |
PUT_MEMORY_SUPPPORTED |
GET_SRAM_OCC_SUPPPORTED |
PUT_SRAM_OCC_SUPPPORTED;
capability[MEMORY_CAPABILITY_START_IDX+1] =
RESERVED_A4_CAPABILITIES;
capability[REGISTER_CAPABILITY_START_IDX] =
GET_REGISTER_SUPPPORTED |
PUT_REGISTER_SUPPPORTED ;
capability[REGISTER_CAPABILITY_START_IDX+1] =
RESERVED_A5_CAPABILITIES;
capability[ARRAY_CAPABILITY_START_IDX] =
CONTROL_FAST_ARRAY_SUPPPORTED |
CONTROL_TRACE_ARRAY_SUPPPORTED;
capability[ARRAY_CAPABILITY_START_IDX+1] =
RESERVED_A6_CAPABILITIES;
capability[INSTRUCTION_CTRL_CAPABILITY_START_IDX] =
CONTROL_INSTRUCTIONS_SUPPPORTED;
capability[INSTRUCTION_CTRL_CAPABILITY_START_IDX+1] =
RESERVED_A7_CAPABILITIES;
capability[GENERIC_CHIPOP_CAPABILITY_START_IDX] =
GET_SBE_FFDC_SUPPPORTED |
SBE_QUIESCE;
capability[GENERIC_CHIPOP_CAPABILITY_START_IDX+1] =
RESERVED_A8_CAPABILITIES;
capability[MPIPL_CAPABILITY_START_IDX] =
ENTER_MPIPL_SUPPORTED |
CONTINUE_MPIPL_SUPPORTED |
STOP_CLOCKS_MPIPL_SUPPORTED;
capability[MPIPL_CAPABILITY_START_IDX+1] =
RESERVED_A9_CAPABILITIES;
}
#endif //__SBEFW_SEEPROM__
#ifndef __SBEFW_SEEPROM__
#endif //not __SBEFW_SEEPROM__
|
