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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: import/chips/p9/procedures/xml/error_info/p9_sbe_common_errors.xml $ -->
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2015,2016 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- This is an automatically generated file. -->
<!-- File: p9_sbe_common_errors.xml. -->
<!-- Halt codes for p9_sbe_common -->
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_ARY_ERR</rc>
<description>ary_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_ARY</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_NSL_ERR</rc>
<description>nsl_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_NSL</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_SL_ERR</rc>
<description>sl_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_SL</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_CPLT_NOT_ALIGNED_ERR</rc>
<description>Chiplet not aligned</description>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_CPLT_OPCG_DONE_NOT_SET_ERR</rc>
<description>Chiplet OPCG_DONE not set after clock start/stop command</description>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_NEST_ARY_ERR</rc>
<description>ary_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_ARY</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_NEST_NSL_ERR</rc>
<description>nsl_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_NSL</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_NEST_SL_ERR</rc>
<description>sl_thold status not matching the expected value in clock start stop sequence</description>
<ffdc>READ_CLK_SL</ffdc>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_READ_ALL_CHECKSTOP_ERR</rc>
<description>Read and or all Checkstop error</description>
<ffdc>READ_ALL_CHECKSTOP</ffdc>
</hwpError>
<!-- ******************************************************************** -->
</hwpErrors>
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