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<!-- IBM_PROLOG_BEGIN_TAG                                                   -->
<!-- This is an automatically generated prolog.                             -->
<!--                                                                        -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml $ -->
<!--                                                                        -->
<!-- OpenPOWER sbe Project                                                  -->
<!--                                                                        -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2019                        -->
<!-- [+] International Business Machines Corp.                              -->
<!--                                                                        -->
<!--                                                                        -->
<!-- Licensed under the Apache License, Version 2.0 (the "License");        -->
<!-- you may not use this file except in compliance with the License.       -->
<!-- You may obtain a copy of the License at                                -->
<!--                                                                        -->
<!--     http://www.apache.org/licenses/LICENSE-2.0                         -->
<!--                                                                        -->
<!-- Unless required by applicable law or agreed to in writing, software    -->
<!-- distributed under the License is distributed on an "AS IS" BASIS,      -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        -->
<!-- implied. See the License for the specific language governing           -->
<!-- permissions and limitations under the License.                         -->
<!--                                                                        -->
<!-- IBM_PROLOG_END_TAG                                                     -->
<hwpErrors>
  <!-- ******************************************************************** -->
  <hwpError>
    <rc>RC_CHECK_MASTER_STOP15_PENDING</rc>
    <description>
      Procedure: p9_sbe_check_master_stop15
      Indicates the targeted core is either running (hasn't started to enter
      a STOP state) or is in transition. This return code would be used by the
      caller (FSP/SBE control loop) to determine whether to continue polling
      for a completed transition.
    </description>

    <ffdc>EX</ffdc>

    <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc>

    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id>
        <target>PU</target>
        <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    </collectRegisterFfdc>
    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id>
        <target>EQ</target>
        <targetType>TARGET_TYPE_EQ</targetType>
    </collectRegisterFfdc>
    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id>
        <target>EC</target>
        <targetType>TARGET_TYPE_CORE</targetType>
    </collectRegisterFfdc>
    <callout>
      <procedure>CODE</procedure>
      <priority>HIGH</priority>
    </callout>
    <callout>
      <procedure>LVL_SUPPORT</procedure>
      <priority>LOW</priority>
    </callout>
    <deconfigure>
      <target>EC</target>
    </deconfigure>
  </hwpError>
  <!-- ******************************************************************** -->
  <hwpError>
    <rc>RC_CHECK_MASTER_STOP15_INVALID_STATE</rc>
    <description>
      Procedure: p9_sbe_check_master_stop15
      Indicates the targeted core is no longer pending entering a STOP state
      but the achieved level is not appropriate.
    </description>

    <ffdc>EX</ffdc>

    <collectFfdc>p9_eq_clear_atomic_lock,EQ</collectFfdc>

    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_PU</id>
        <target>PU</target>
        <targetType>TARGET_TYPE_PROC_CHIP</targetType>
    </collectRegisterFfdc>
    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_EQ</id>
        <target>EQ</target>
        <targetType>TARGET_TYPE_EQ</targetType>
    </collectRegisterFfdc>
    <collectRegisterFfdc>
        <id>CHECK_MASTER_STOP15_FFDC_REGS_EC</id>
        <target>EC</target>
        <targetType>TARGET_TYPE_CORE</targetType>
    </collectRegisterFfdc>
    <callout>
      <procedure>CODE</procedure>
      <priority>HIGH</priority>
    </callout>
    <callout>
      <procedure>LVL_SUPPORT</procedure>
      <priority>LOW</priority>
    </callout>
    <deconfigure>
      <target>EC</target>
    </deconfigure>
  </hwpError>
  <!-- ******************************************************************** -->
  <hwpError>
    <sbeError/>
    <rc>RC_CHECK_MASTER_STOP15_DEADMAN_TIMEOUT</rc>
    <description>
      SBE deadman timer fired with reason set in DEADMAN_TIMEOUT_REASON
    </description>
    <ffdc>DEADMAN_TIMEOUT_REASON</ffdc>
    <ffdc>CORE_TARGET</ffdc>
    <ffdc>PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR</ffdc>
    <ffdc>PU_OCB_OCI_QCSR__PU_OCB_OCI_QSSR</ffdc>
    <ffdc>EQ_PPM_SSHSRC__EX_CME_SCOM_LFIR</ffdc>
    <ffdc>EX_CME_SCOM_SICR_SCOM</ffdc>
    <ffdc>EX_CME_LCL_SISR_SCOM</ffdc>
    <ffdc>EQ_ATOMIC_LOCK_REG</ffdc>
    <ffdc>C0_PPM_SSHSRC__C1_PPM_SSHSRC</ffdc>
    <ffdc>SGPE_XSR__IAR</ffdc>
    <ffdc>SGPE_IR__EDR</ffdc>
    <ffdc>SGPE_LR__SPRG0</ffdc>
    <ffdc>SGPE_SRR0__SRR1</ffdc>
    <ffdc>CME_XSR__IAR</ffdc>
    <ffdc>CME_IR__EDR</ffdc>
    <ffdc>CME_LR__SPRG0</ffdc>
    <ffdc>CME_SRR0__SRR1</ffdc>
    <callout>
      <procedure>CODE</procedure>
      <priority>HIGH</priority>
    </callout>
    <callout>
      <procedure>LVL_SUPPORT</procedure>
      <priority>LOW</priority>
    </callout>
    <deconfigure>
      <target>CORE_TARGET</target>
    </deconfigure>
  </hwpError>
  <!-- ******************************************************************** -->
</hwpErrors>
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