blob: bc35618b619b9fa5ae4a18661a266ab66f0ae987 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
|
<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml $ -->
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<hwpErrors>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_CHECK_MASTER_STOP15_PENDING</rc>
<description>
Procedure: p9_sbe_check_master_stop15
Indicates the targeted core is either running (hasn't started to enter
a STOP state) or is in transition. This return code would be used by the
caller (SBE control loop) to determine whether to continue polling for a
completed transition.
Note: STOP 11 and STOP 15 are equivalent for POWER9.
</description>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<rc>RC_CHECK_MASTER_STOP15_INVALID_STATE</rc>
<description>
Procedure: p9_sbe_check_master_stop15
Indicates the targeted core is no longer pending entering a STOP state
but the achieved level is not appropriate.
</description>
<ffdc>CORE_TARGET</ffdc>
<ffdc>STOP_HISTORY</ffdc>
<callout>
<procedure>CODE</procedure>
<priority>HIGH</priority>
</callout>
<callout>
<procedure>LVL_SUPPORT</procedure>
<priority>LOW</priority>
</callout>
<deconfigure>
<target>CORE_TARGET</target>
</deconfigure>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
<rc>RC_CHECK_MASTER_STOP15_FAILED</rc>
<description>
Indicates the targeted core(s) are no longer pending entering a STOP state
but the achieved level is not appropriate, or the deadman loop timed out.
</description>
<ffdc>SBE_CHK_MASTER_STOP15_RC</ffdc>
<ffdc>CORE_TARGET</ffdc>
<ffdc>PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR</ffdc>
<ffdc>PU_OCB_OCI_QCSR__PU_OCB_OCI_QSSR</ffdc>
<ffdc>EQ_PPM_SSHSRC__EX_CME_SCOM_LFIR</ffdc>
<ffdc>EX_CME_SCOM_SICR_SCOM</ffdc>
<ffdc>EX_CME_LCL_SISR_SCOM</ffdc>
<ffdc>EQ_ATOMIC_LOCK_REG</ffdc>
<ffdc>C0_PPM_SSHSRC__C1_PPM_SSHSRC</ffdc>
<ffdc>SGPE_XSR__IAR</ffdc>
<ffdc>SGPE_IR__EDR</ffdc>
<ffdc>SGPE_LR__SPRG0</ffdc>
<ffdc>SGPE_SRR0__SRR1</ffdc>
<ffdc>CME_XSR__IAR</ffdc>
<ffdc>CME_IR__EDR</ffdc>
<ffdc>CME_LR__SPRG0</ffdc>
<ffdc>CME_SRR0__SRR1</ffdc>
<callout>
<procedure>LVL_SUPPORT</procedure>
<priority>LOW</priority>
</callout>
<deconfigure>
<target>CORE_TARGET</target>
</deconfigure>
</hwpError>
<!-- ******************************************************************** -->
</hwpErrors>
|