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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/error_info/p9_hcd_core_stopclocks_errors.xml $ -->
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!-- Error definitions for p9_hcd_cache_startclocks procedures -->
<hwpErrors>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PMPROC_COREPCBMUX_TIMEOUT</rc>
<description>
polling for pcb mux grant timed out.
</description>
<ffdc>CMESISR</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PMPROC_CORECLKSYNCDROP_TIMEOUT</rc>
<description>
core clock sync done drop timed out.
</description>
<ffdc>COREPPMCACSR</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PMPROC_CORECLKSTOP_FAILED</rc>
<description>
core clock stop failed.
</description>
<ffdc>CORECLKSTAT</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_PMPROC_CORECLKSTOP_TIMEOUT</rc>
<description>
core clock stop timed out.
</description>
<ffdc>CORECPLTSTAT</ffdc>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_CORE_STOPCLKS_PGPE_HALT_TIMEOUT</rc>
<description>
A timeout occured while waiting the PGPE to halt
</description>
<ffdc>CHIP</ffdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_CORE_STOPCLKS_SGPE_HALT_TIMEOUT</rc>
<description>
A timeout occured while waiting the SGPE to halt
</description>
<ffdc>CHIP</ffdc>
<callout>
<target>CHIP</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_CORE_STOPCLKS_ATOMIC_LOCK_FAIL</rc>
<description>
Failed attempt to clear the atomic lock to the cache chiplet
</description>
<ffdc>EQ</ffdc>
<callout>
<target>EQ</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- ********************************************************************* -->
<hwpError>
<rc>RC_CORE_STOPCLKS_CME_HALT_TIMEOUT</rc>
<description>
A timeout occured while waiting a CME to halt
</description>
<ffdc>EX</ffdc>
<callout>
<target>EX</target>
<priority>HIGH</priority>
</callout>
</hwpError>
<!-- ********************************************************************* -->
</hwpErrors>
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