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<!-- IBM_PROLOG_BEGIN_TAG -->
<!-- This is an automatically generated prolog. -->
<!-- -->
<!-- $Source: src/import/chips/p9/procedures/xml/attribute_info/p9_hcode_image_build_attributes.xml $ -->
<!-- -->
<!-- OpenPOWER sbe Project -->
<!-- -->
<!-- Contributors Listed Below - COPYRIGHT 2016,2017 -->
<!-- [+] International Business Machines Corp. -->
<!-- -->
<!-- -->
<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
<!-- you may not use this file except in compliance with the License. -->
<!-- You may obtain a copy of the License at -->
<!-- -->
<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
<!-- -->
<!-- Unless required by applicable law or agreed to in writing, software -->
<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
<!-- implied. See the License for the specific language governing -->
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
<!--nest_attributes.xml-->
<attributes>
<!-- ********************************************************************** -->
<attribute>
<id>ATTR_FUSED_CORE_MODE</id>
<targetType>TARGET_TYPE_SYSTEM</targetType>
<description>
Summarizes the fused status of cores. This is same for all P9 chips
in the system. If a core is in a fused state, attribute should read 1
else zero. It needs to be populated during ipl but before istep 15.
</description>
<valueType>uint8</valueType>
<enum> CORE_UNFUSED = 0x0, CORE_FUSED = 0x1 </enum>
<platInit/>
</attribute>
<attribute>
<id>ATTR_HOMER_PHYS_ADDR</id>
<targetType>TARGET_TYPE_PROC_CHIP</targetType>
<description>
Physical real address of the HOMER image for this chip. Used to
tell the CME where this HOMER image will be placed. Must be
aligned to a 4MB boundary
</description>
<valueType>uint64</valueType>
<platInit/>
</attribute>
</attributes>
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