1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
//------------------------------------------------------------------------------
/// @file p9_sbe_npll_setup.C
///
/// @brief scan initialize level 0 & 1 PLLs
//------------------------------------------------------------------------------
// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
// *HWP Level : 2
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
//## auto_generated
#include "p9_sbe_npll_setup.H"
//## auto_generated
#include "p9_const_common.H"
#include <p9_perv_scom_addresses.H>
#include <p9_perv_scom_addresses_fld.H>
enum P9_SBE_NPLL_SETUP_Private_Constants
{
NS_DELAY = 5000000, // unit is nano seconds
SIM_CYCLE_DELAY = 1000 // unit is sim cycles
};
static fapi2::ReturnCode p9_sbe_npll_setup_sectorbuffer_pulsemode_settings(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip);
fapi2::ReturnCode p9_sbe_npll_setup(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
fapi2::buffer<uint64_t> l_read_reg;
uint8_t l_read_attr = 0;
uint8_t l_nest_bypass = 0;
uint8_t l_attr_ss_filter = 0;
uint8_t l_attr_cp_filter = 0;
uint8_t l_attr_io_filter = 0;
fapi2::buffer<uint64_t> l_data64_root_ctrl8;
fapi2::buffer<uint64_t> l_data64_perv_ctrl0;
FAPI_INF("p9_sbe_npll_setup: Entering ...");
FAPI_DBG("Sector buffer strength and pulse mode setup");
FAPI_TRY(p9_sbe_npll_setup_sectorbuffer_pulsemode_settings(i_target_chip));
FAPI_DBG("Reading ROOT_CTRL8 register value");
//Getting ROOT_CTRL8 register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8)); //l_data64_root_ctrl8 = PIB.ROOT_CTRL8
FAPI_DBG("Reading ATTR_SS_FILTER_BYPASS, ATTR_CP_FILTER_BYPASS, ATTR_IO_FILTER_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SS_FILTER_BYPASS, i_target_chip,
l_attr_ss_filter));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CP_FILTER_BYPASS, i_target_chip,
l_attr_cp_filter));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_IO_FILTER_BYPASS, i_target_chip,
l_attr_io_filter));
FAPI_DBG("SS,CP and IO filter configuration 1.ATTR_SS_FILTER_BYPASS: %#018lX 2.ATTR_CP_FILTER_BYPASS: %#018lX 3.ATTR_IO_FILTER_BYPASS: %#018lX",
l_attr_ss_filter, l_attr_cp_filter, l_attr_io_filter);
if (l_attr_ss_filter == 0x0 )
{
FAPI_DBG("Drop PLL test enable for Spread Spectrum PLL");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_SS0_PLL_TEST_EN = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_TEST_EN>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
FAPI_DBG("Release SS PLL reset");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_SS0_PLL_RESET = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_RESET>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
FAPI_DBG("check SS PLL lock");
//Getting PLL_LOCK_REG register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
FAPI_ASSERT(l_read_reg.getBit<0>(),
fapi2::SS_PLL_LOCK_ERR()
.set_MASTER_CHIP(i_target_chip)
.set_SS_PLL_READ(l_read_reg),
"ERROR:SS PLL LOCK NOT SET");
FAPI_DBG("Release SS PLL Bypass");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_SS0_PLL_BYPASS = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_SS0_PLL_BYPASS>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
}
if ( l_attr_cp_filter == 0x0 )
{
FAPI_DBG("Drop PLL test enable for CP Filter PLL");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT1_PLL_TEST_EN = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_TEST_EN>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
FAPI_DBG("Release CP Filter PLL reset");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT1_PLL_RESET = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_RESET>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
//Getting PLL_LOCK_REG register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
FAPI_ASSERT(l_read_reg.getBit<1>(),
fapi2::CP_FILTER_PLL_LOCK_ERR()
.set_MASTER_CHIP(i_target_chip)
.set_CP_FILTER_PLL_READ(l_read_reg),
"ERROR:CP FILTER PLL LOCK NOT SET");
FAPI_DBG("Release CP filter PLL Bypass Signal");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT1_PLL_BYPASS = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT1_PLL_BYPASS>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
}
if ( l_attr_io_filter == 0x0 )
{
FAPI_DBG("Drop PLL test enable for IO Filter PLL");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT0_PLL_TEST_EN = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_TEST_EN>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
FAPI_DBG("Release IO Filter PLL reset");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT0_PLL_RESET = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_RESET>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
FAPI_DBG("check PLL lock for CP Filter PLL , Check PLL lock fir IO Filter PLL");
//Getting PLL_LOCK_REG register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
FAPI_ASSERT(l_read_reg.getBit<2>(),
fapi2::IO_FILTER_PLL_LOCK_ERR()
.set_MASTER_CHIP(i_target_chip)
.set_IO_FILTER_PLL_READ(l_read_reg),
"ERROR:IO FILTER PLL LOCK NOT SET");
FAPI_DBG("Release IO filter PLL Bypass Signal");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_FILT0_PLL_BYPASS = 0
l_data64_root_ctrl8.clearBit<PERV_ROOT_CTRL8_SET_TP_FILT0_PLL_BYPASS>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
}
FAPI_DBG("Reading ATTR_NEST_MEM_X_O_PCI_BYPASS");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_NEST_MEM_X_O_PCI_BYPASS, i_target_chip, l_nest_bypass),
"Error from FAPI_ATTR_GET (ATTR_NEST_MEM_X_O_PCI_BYPASS)");
if ( l_nest_bypass == 0x0 )
{
FAPI_DBG("Drop PLL test enable for Nest PLL");
//Setting PERV_CTRL0 register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
l_data64_perv_ctrl0));
//PIB.PERV_CTRL0.TP_PLL_TEST_EN_DC = 0
l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLL_TEST_EN_DC>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
l_data64_perv_ctrl0));
}
FAPI_DBG("Reading ATTR_MC_SYNC_MODE");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_MC_SYNC_MODE, i_target_chip, l_read_attr));
if ( l_read_attr == 1 )
{
FAPI_DBG("Set MUX to Nest Clock input");
//Setting ROOT_CTRL8 register value
//PIB.ROOT_CTRL8.TP_PLL_CLKIN_SEL4_DC = 1
l_data64_root_ctrl8.setBit<PERV_ROOT_CTRL8_SET_TP_PLL_CLKIN_SEL4_DC>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL8_SCOM,
l_data64_root_ctrl8));
}
if ( l_nest_bypass == 0x0 )
{
FAPI_DBG("Release Nest PLL reset");
//Setting PERV_CTRL0 register value
//PIB.PERV_CTRL0.TP_PLLRST_DC = 0
l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLRST_DC>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
l_data64_perv_ctrl0));
fapi2::delay(NS_DELAY, SIM_CYCLE_DELAY);
FAPI_DBG("check NEST PLL lock");
//Getting PLL_LOCK_REG register value
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_PLL_LOCK_REG,
l_read_reg)); //l_read_reg = PERV.PLL_LOCK_REG
FAPI_ASSERT(l_read_reg.getBit<3>(),
fapi2::NEST_PLL_ERR()
.set_MASTER_CHIP(i_target_chip)
.set_NEST_PLL_READ(l_read_reg)
.set_SS_FILTER_BYPASS_STATUS(l_attr_ss_filter)
.set_CP_FILTER_BYPASS_STATUS(l_attr_cp_filter)
.set_IO_FILTER_BYPASS_STATUS(l_attr_io_filter),
"ERROR:NEST PLL LOCK NOT SET");
FAPI_DBG("Release PLL bypass2");
//Setting PERV_CTRL0 register value
//PIB.PERV_CTRL0.TP_PLLBYP_DC = 0
l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_PLLBYP_DC>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM,
l_data64_perv_ctrl0));
}
l_read_reg.flush<1>();
// Clear Perv pcb slave error register
// Clearing mask bit in pcb slave config register [bit 12] to allow unlock error
// to propagate to Pervasive Lfir [ bit 21]
if ( l_nest_bypass == 0x0 && l_attr_cp_filter == 0x0 && l_attr_ss_filter == 0x0 && l_attr_io_filter == 0x0 )
{
FAPI_DBG(" Reset PCB error reg");
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ERROR_REG, l_read_reg));
FAPI_DBG(" Unmasking pll unlock error in Pcb slave config reg");
FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SLAVE_CONFIG_REG, l_read_reg));
l_read_reg.clearBit<12>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SLAVE_CONFIG_REG, l_read_reg));
}
FAPI_INF("p9_sbe_npll_setup: Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
/// @brief Setup sector buffer strength and pulse mode
///
/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
/// @return FAPI2_RC_SUCCESS if success, else error code.
static fapi2::ReturnCode p9_sbe_npll_setup_sectorbuffer_pulsemode_settings(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target_chip)
{
fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> l_sys;
fapi2::buffer<uint64_t> l_data64_perv_ctrl1;
fapi2::buffer<uint8_t> l_attr_buffer_strength = 0;
fapi2::buffer<uint8_t> l_attr_pulse_mode_enable = 0;
fapi2::buffer<uint8_t> l_attr_pulse_mode_value = 0;
FAPI_INF("p9_sbe_npll_setup_sectorbuffer_pulsemode_settings:Entering ...");
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECTOR_BUFFER_STRENGTH, l_sys,
l_attr_buffer_strength));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_ENABLE, l_sys,
l_attr_pulse_mode_enable));
FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PULSE_MODE_VALUE, l_sys,
l_attr_pulse_mode_value));
FAPI_TRY(fapi2::getScom(i_target_chip , PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1));
FAPI_DBG("Sector buffer strength");
l_data64_perv_ctrl1.insertFromRight< PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC,
PERV_PERV_CTRL1_TP_SEC_BUF_DRV_STRENGTH_DC_LEN >(l_attr_buffer_strength);
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1));
FAPI_DBG("Pulse mode enable & pulse mode");
if (l_attr_pulse_mode_enable.getBit<7>())
{
l_data64_perv_ctrl1.setBit<PERV_PERV_CTRL1_TP_CLK_PULSE_ENABLE_DC>();
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1));
l_data64_perv_ctrl1.insertFromRight< PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC,
PERV_PERV_CTRL1_TP_CLK_PULSE_MODE_DC_LEN >(l_attr_pulse_mode_value);
FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL1_SCOM, l_data64_perv_ctrl1));
}
FAPI_INF("p9_sbe_npll_setup_sectorbuffer_pulsemode_settings:Exiting ...");
fapi_try_exit:
return fapi2::current_err;
}
|
