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/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/import/chips/p9/procedures/hwp/core/p9_hcd_core_chiplet_init.C $ */
/* */
/* OpenPOWER sbe Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2017 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
///
/// @file p9_hcd_core_chiplet_init.C
/// @brief Core Flush/Initialize
///
/// Procedure Summary:
/// Switch the core glitchless mux to allow DPLL clocks on the clock grid
/// Clocking:
/// - setup controls based on DPLL frequency
/// - assert PM sync_enable (4x core, 2 x L2),
/// DCCs and SkewAdjust starts aligning clocks
/// Scan0 flush all chiplet rings except VITAL, GPTR and TIME
// *HWP HWP Owner : David Du <daviddu@us.ibm.com>
// *HWP Backup HWP Owner : Greg Still <stillgs@us.ibm.com>
// *HWP FW Owner : Prem Shanker Jha <premjha2@in.ibm.com>
// *HWP Team : PM
// *HWP Consumed by : SBE:CME
// *HWP Level : 3
//------------------------------------------------------------------------------
// Includes
//------------------------------------------------------------------------------
#include <p9_quad_scom_addresses.H>
#include <p9_perv_sbe_cmn.H>
#include <p9_hcd_common.H>
#include "p9_hcd_core_chiplet_init.H"
//------------------------------------------------------------------------------
// Constant Definitions
//------------------------------------------------------------------------------
//------------------------------------------------------------------------------
// Procedure: Core Flush/Initialize
//------------------------------------------------------------------------------
fapi2::ReturnCode
p9_hcd_core_chiplet_init(
const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target)
{
FAPI_INF(">>p9_hcd_core_chiplet_init");
FAPI_INF("<<p9_hcd_core_chiplet_init");
return fapi2::current_err;
}
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