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//------------------------------------------------------------------------------
/// @file p9_sbe_chiplet_pll_initf.H
///
/// @brief procedure for scan initializing PLL config bits for L2 and L3 plls
// *!
// *! OWNER NAME : Abhishek Agarwal Email: abagarw8@in.ibm.com
// *! BACKUP NAME : srinivas naga Email: srinivan@in.ibm.com
//------------------------------------------------------------------------------
// *HWP HWP Owner : Abhishek Agarwal <abagarw8@in.ibm.com>
// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com>
// *HWP Team : Perv
// *HWP Level : 1
// *HWP Consumed by : SBE
//------------------------------------------------------------------------------
#ifndef _P9_SBE_CHIPLET_PLL_INITF_H_
#define _P9_SBE_CHIPLET_PLL_INITF_H_
#include <fapi2.H>
typedef fapi2::ReturnCode (*p9_sbe_chiplet_pll_initf_FP_t)(
const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> &);
/// @brief load the pll config settings for L2 AND L3 plls
///
/// @param[in] i_target_chip Reference to TARGET_TYPE_PROC_CHIP target
/// @return FAPI2_RC_SUCCESS if success, else error code.
extern "C"
{
fapi2::ReturnCode p9_sbe_chiplet_pll_initf(const
fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP> & i_target_chip);
}
#endif
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