summaryrefslogtreecommitdiffstats
path: root/src
Commit message (Expand)AuthorAgeFilesLines
...
* Modifying ATTRs for memory power thermalJacob Harvey2018-12-171-23/+55
* Implement MRW attributes; dram_clks, db_util, 2n_modeBrian Silver2018-12-171-15/+0
* Fix eff_config, remove custom_dimmJacob Harvey2018-12-171-39/+2
* Fixed eff_config attr generationStephen Glancy2018-12-171-1/+1
* Adding defaults for DRAM dll_reset and dll_enableLouis Stermole2018-12-171-1/+2
* Changes related to RTT VPD settingsBrian Silver2018-12-171-61/+1
* Add consumption of IBT from VPD and place in RCD7xBrian Silver2018-12-171-19/+0
* Change ODT R/W to take values from VPDBrian Silver2018-12-171-32/+0
* Change MSS_VOLT to MSS_VOLT_VDDRJacob Harvey2018-12-171-5/+5
* Fix p9_mss_utils_to_throttle, create throttles API, attribute cleanupAndre Marin2018-12-171-43/+16
* Modify SPD blob and eff-config hardcoding to match VBUAndre Marin2018-12-171-56/+0
* Packaging of memory vpd on Nimbus, MCA->MCSwhs2018-12-171-112/+0
* Added initToZero tag for all memory attributesJacob Harvey2018-12-171-0/+225
* Add eff_config functionality needed for RIT, fix cas_latency bug & attr filesAndre Marin2018-12-171-393/+36
* Add override attributes for memory vpd accessDan Crowell2018-12-171-0/+104
* Remove whitespace that breaks HB attribute compilerDan Crowell2018-12-171-1/+1
* Fix throttle procedure & MSS attribute clean upAndre Marin2018-12-171-2940/+178
* Add L2 p9_mss_scrubBrian Silver2018-12-171-348/+0
* Modify freq & dep. files. Add cas latency & unit testsAndre Marin2018-12-171-5/+7
* Add dp16 io tx dll/vreg configBrian Silver2018-12-171-0/+2
* Add mss throttle files L1Andre Marin2018-12-171-494/+77
* Change DIMM_SIZE from 8 bits to 32 bitsBrian Silver2018-12-171-10/+3
* Modify spd_decoder, eff_config, unit tests. Modify dependent filesAndre Marin2018-12-171-394/+18
* Add mcbist L2 functionBrian Silver2018-12-171-20/+29
* Add PHY RC class, update setup cal for 2D wc/rcBrian Silver2018-12-171-3/+14
* Initial commit of memory subsystemBrian Silver2018-12-171-0/+7294
* PGPE: WOV Attributes (1/3)Rahul Batra2018-12-142-0/+368
* SMF: Defined new attribute to store unsecure HOMER's base address.Prem Shanker Jha2018-12-121-0/+16
* Revert "Self Save: Fixed bugs pertaining to SPR self save."RAJA DAS2018-12-121-16/+0
* SMF: Defined new attribute to store unsecure HOMER's base address.Prem Shanker Jha2018-12-121-0/+16
* Remove unused code from SBESachin Gupta2018-12-103-18/+18
* Support for renaming loader_data section to pibmemrepair_data sectionRaja Das2018-12-031-3/+3
* Re-used loader_data section to pibmem repair scom data for AxoneRaja Das2018-12-031-22/+22
* Leave scratch valid bits alone to allow HB to queryDean Sanner2018-11-291-15/+4
* Removed dual compilation of pibmem_repair.SRaja Das2018-11-281-6/+0
* Adding omi_init procedures.Ben Gass2018-11-251-0/+34
* Adding p9a_ocmb_enableBen Gass2018-11-201-0/+12
* test: Temporarily disable testArrayAccessJoachim Fenkes2018-11-151-1/+1
* SBE logs on serial consolespashabk-in2018-11-133-12/+64
* Add Axone targets to fapi error utilitiesDan Crowell2018-11-121-10/+17
* HW471413 Aggressive Uncle: disable ERAT thread sharingJenny Huynh2018-11-111-5/+12
* fapi2: Use correct RingMode typeJoel Stanley2018-11-011-2/+2
* p9_sbe_tp_chiplet_init: Fix missing semicolonsJoel Stanley2018-11-011-2/+2
* Revert "Clear INT_CQ related firs after completing sync_reset in MPIPL"Christian R. Geddes2018-11-012-51/+0
* Clear INT_CQ related firs after completing sync_reset in MPIPLChristian Geddes2018-11-012-0/+51
* Instruction machine check ISR updatedRaja Das2018-10-311-7/+5
* Img Build: HOMER changes for SMF and SPR self save.Prem Shanker Jha2018-10-291-0/+24
* Enabling ipmi console accessspashabk-in2018-10-2510-1/+457
* PM: Fixed handling of CME LFIR mask during PM complex reset.Prem Shanker Jha2018-10-241-1/+1
* Only save the CME FIR Masks after they have been setup onceDan Crowell2018-10-241-0/+1
OpenPOWER on IntegriCloud