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* H-code ddLevel support - Front-end hooks for user and back-end codes.Claus Michael Olsen2017-05-124-53/+274
* Add DLL workaround and unit testsAndre Marin2017-05-121-54/+73
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-112-16/+150
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-05-113-37/+308
* Implementing Michael Floyds improvements.Michael Koch2017-05-111-5/+37
* Added DQS alignment workaroundStephen Glancy2017-05-111-0/+19
* Enablement of n3_br_fure ring for Nimbus DD2Sumit Kumar2017-05-113-7/+9
* dd2 initsShelton Leung2017-05-111-34/+103
* p9.xbus.pll.scan.initfile -- restore full frequency settings for Nimbus DD2+Joe McGill2017-05-111-0/+18
* Update INT DD2 initfilesDavid Kauer2017-05-111-0/+17
* Updates for P9 NX DD2 initfilesChris Hanudel2017-05-111-54/+72
* Setting up nmmu lco targets/min based on valid exsJenny Huynh2017-05-111-1/+51
* ADU Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-118-224/+347
* PBA Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-118-139/+307
* p9_nv_ref_clk_enable -- shift NV refclock field programmingJoe McGill2017-05-111-2/+9
* derate NVLINK frequency for Nimbus DD1Joe McGill2017-05-051-0/+17
* Performance updates for HW409069Luke Murray2017-05-051-0/+25
* Reserving HTM QueuesThi Tran2017-05-051-0/+17
* WOF: Additional fields needed in OCC Pstate Parameter block for WOFPrasad Bg Ranganath2017-05-051-0/+18
* p9_mss_setup_bars -- customize interleave granularityJoe McGill2017-05-042-0/+36
* p9_sbe_attributes.xml -- add entries for effective FBC IDsJoe McGill2017-05-041-0/+8
* p9_sbe_chiplet_reset: Revert NX_1 hang pulse back to 34sJoachim Fenkes2017-05-042-4/+2
* Change RD_CTR workaround val and update attr nameJacob Harvey2017-04-281-8/+8
* L3 initfile updatesAlex Taft2017-04-282-23/+18
* Adding HW401552 to cxa initfile to workaround clockgating bugJenny Huynh2017-04-281-0/+17
* Fixing CME TOR allocation bug in ring_apply and TOR APIClaus Michael Olsen2017-04-282-99/+97
* PM: Added support for scanning of eq_inex ring.Prem Shanker Jha2017-04-282-2/+0
* PM: Added support for PBI EQ async boundary crossing latchesPrem Shanker Jha2017-04-283-10/+33
* WOF: VRM timing, WOF and VDM enblement attributes additionsPrasad Bg Ranganath2017-04-281-1/+130
* Eff_config, volt, freq for p9cLuke Mulkey2017-04-281-5/+9
* changed hang to recoverable form checkstopEmmanuel Sacristan2017-04-281-2/+2
* Disable cp_me from the L3 for Nimbus DD1 and DD2.0.Luke Murray2017-04-281-0/+17
* p9_sbe_set_lqa and p9_sbe_hb_structures changed owner to JoshCHRISTINA L. GRAVES2017-04-281-2/+2
* Initf proc updatesAnusha Reddy Rangareddygari2017-04-284-161/+471
* INT scan initfile change to add workaround for HW408972Jenny Huynh2017-04-281-0/+18
* Updating HW363605 workaround to be applied to all chipsLuke Murray2017-04-281-17/+0
* Add NCU/L3 dials for HW396230 to p9.ncu.scom.initfileCHRISTINA L. GRAVES2017-04-284-5/+54
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-282-22/+62
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2017-04-201-0/+18
* Fixing SGPE TOR allocation bug in ring_applyClaus Michael Olsen2017-04-191-0/+1
* p9_pstate_param_blk: Define VFRT table and initialize the dataPrasad Bg Ranganath2017-04-191-0/+37
* PM: Resonant Clocking Enablement - InfrastructureChristopher M. Riedl2017-04-191-6/+6
* using literal definitionsSoma BhanuTej2017-04-192-61/+57
* PK move global data to .sdata/.sbss sections to reduce code sizeDoug Gilbert2017-04-196-13/+17
* p9_sbe_startclock_chiplets updatesAnusha Reddy Rangareddygari2017-04-191-0/+21
* Add unique FAPI RC per PIB RCSantosh Puranik2017-04-181-1/+43
* STOP: Enable CHTMYue Du2017-04-181-0/+38
* PK DEC timer interrupts too close togetherDoug Gilbert2017-04-182-10/+19
* Added read ctr bad delay workaroundStephen Glancy2017-04-181-0/+17
* Updating optimal larx/stcx dials for performanceLuke Murray2017-04-181-0/+24
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