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* Halt on zero instruction/load/store addressAdam Hale2017-08-112-2/+9
* Update p9_sbe_load_bootloader Hwp to receive the addr-key stash-2Raja Das2017-08-114-1/+50
* p9_sbe_common -- update TP LFIR to match RAS XML v95Joe McGill2017-08-101-1/+1
* Fakering and NO_DE_SWIZZLE can not go together.Sunil Kumar2017-08-091-0/+9
* Adding p9 security blacklist and whitelist filespashabk-in2017-08-081-0/+824
* Centaur istep 11 supportThi Tran2017-08-082-0/+295
* Modified gen_accessors script for greater supportAndre Marin2017-08-082-0/+19
* Level 3: For various PM HWPSangeetha T S2017-08-081-0/+1
* PM: Level3 Special Wakeup Hardware ProcedurePrem Shanker Jha2017-08-081-0/+45
* L3 Update - p9_ram_core HWPsThi Tran2017-08-083-85/+162
* L3 Update - p9_thread_control HWPThi Tran2017-08-073-275/+241
* Characterization Default ImageAdam Hale2017-08-071-2/+4
* PSTATE: PGPE_Flags-ATTR_PGPE_HCODE_FUNCTION_ENABLE FixRahul Batra2017-08-071-2/+1
* Compile failure in cronus envRichard J. Knight2017-08-071-1/+1
* L3 update -- p9_sbe_load_bootloaderJoe McGill2017-08-074-365/+575
* B1814616 - hwsvd sig:11 core dump on zzfp247Richard J. Knight2017-08-023-21/+72
* Removed GPE halt workaround from p9_pm_check_quiesceSachin Gupta2017-08-021-21/+0
* Enabled p9_suspend_powman.CSachin Gupta2017-08-021-0/+1
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2017-07-313-179/+216
* p9.int.scom.initfile -- mask SUE FIR for Nimbus DD2Joe McGill2017-07-281-0/+17
* Add additional dials to risklevelNick Klazynski2017-07-281-0/+17
* p9.obus.pll.scan.initfile -- adjust Nimbus DD2 POR to 25gbsJoe McGill2017-07-281-2/+23
* p9_sbe_chiplet_pll_initf: Level 3Joachim Fenkes2017-07-263-3/+7
* p9_sbe_npll_setup: Level 3Joachim Fenkes2017-07-263-5/+61
* p9_sbe_npll_initf: Level 3Joachim Fenkes2017-07-263-4/+8
* p9_hcd_cache_dcc_skewadjust_setup.CAnusha Reddy Rangareddygari2017-07-261-2/+2
* Fixing mmu epsilon write cycles valueJenny Huynh2017-07-261-6/+0
* Remove reset_dll from scominit, enable delay line tap pointsAndre Marin2017-07-261-3/+20
* p9.npu.scom.initfile -- FIR updates to align with RAS XML documentationJoe McGill2017-07-261-0/+35
* TP, Nest FIR updates -- DD2 updates to match RAS XMLJoe McGill2017-07-264-9/+42
* GPTR/Overlays stage-2 supportSumit Kumar2017-07-264-13/+24
* Set size of enum CHIPLET_TYPESachin Gupta2017-07-251-1/+1
* p9_sbe_tp_chiplet_init3: Level 3Joachim Fenkes2017-07-253-42/+76
* L3 Update - p9_l2/l3_flush.CThi Tran2017-07-246-223/+199
* Suspend HWP Halted CheckingAdam Hale2017-07-241-58/+72
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2017-07-243-59/+154
* Removed unnecessary FFDCSachin Gupta2017-07-202-13/+1
* FAPI2 - Enable register ffdc supportRichard J. Knight2017-07-201-1/+4
* L3 Level changes in p9_avbus_lib.CPrasad Bg Ranganath2017-07-201-1/+4
* Istep4: procedures upgrade to level3Yue Du2017-07-2061-790/+842
* p9_sbe_check_master_stop15: Level 3Joachim Fenkes2017-07-204-23/+38
* Add pm_check_quiesce function to list of sbe_check_quiesce functioncrgeddes2017-07-192-0/+65
* Optimized PPE FFDC collection frameworkAmit Tendolkar2017-07-199-188/+174
* Make freq_x_mhz attribute writeablecrgeddes2017-07-191-1/+1
* PGPE: WOF Phase 2Rahul Batra2017-07-191-0/+18
* NMMU FIR, RAS XML updates for Nimbus DD2Joe McGill2017-07-191-18/+18
* updates for thread control, ramming with STOP enabledJoe McGill2017-07-192-65/+42
* chip XOR swap -- use absolute fabric group ID to form bootloader load addressJoe McGill2017-07-194-11/+25
* Dumy commit to work-around auto-mirror issue from 38781Amit Tendolkar2017-07-181-0/+1
* Have SBE set PSSCR in fused core modeDean Sanner2017-07-171-7/+18
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