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* L3 update - p9_sbe_check_quiesceThi Tran2017-09-053-289/+403
* STOP: Add Core quiesce workaround to CME Fit TimerYue Du2017-09-041-29/+5
* Updating target name and chiplet rangesspashabk-in2017-09-041-824/+824
* Ensure SGPE is disabled and ensure writes are enabled during pm_suspendcrgeddes2017-08-312-13/+28
* PM: Add atrribute control to SGPE for Core Periodic QuiesceGreg Still2017-08-312-3/+26
* Add OBUS pll freq list for Axone and p9n dd2.2Ben Gass2017-08-311-0/+14
* Enabling PWC for Nimbus DD2.0+ and Cumulus DD1.0+Jenny Huynh2017-08-311-6/+0
* TOR magic header commit: Primer for commit 35372Claus Michael Olsen2017-08-301-0/+31
* Add Periodic Core Quiesce Disable Scom PropagationAdam Hale2017-08-291-0/+2
* p9_sbe_tracearray: Add chip type detection to support changed p9c MC tracesJoachim Fenkes2017-08-291-47/+88
* compact suspend ffdcAdam Hale2017-08-285-114/+114
* HW417560 NCU master tlbie settings tuningJenny Huynh2017-08-251-2/+15
* p9_sbe_scominit -- unmask PB EAST FIR 31 for hypervisor TIJoe McGill2017-08-251-1/+1
* Move clearing of CPMMR PPM WRITE DISABLE so it called on all func corescrgeddes2017-08-241-7/+9
* Support the PIB abort condition on PPE platformCHRISTINA L. GRAVES2017-08-231-32/+45
* Optimise RamCore put_reg & get_regspashabk-in2017-08-231-261/+194
* PGPE TraceAdam Hale2017-08-232-0/+2
* PM: PGPE Flags Struct FixRahul Batra2017-08-231-2/+2
* PM: Remove VDM check from p9_hcd_cache_stopclocksGreg Still2017-08-221-13/+13
* Optimize p9_adu_coherent_utilsspashabk-in2017-08-211-37/+28
* Temp commit to enable manual mirror of new files to ppeAmit Tendolkar2017-08-212-0/+304
* Fix bug in npu quiesce sequencecrgeddes2017-08-181-57/+49
* Clear disable_ppm_writes bit on CPPM register prior to setting PFDLYcrgeddes2017-08-182-0/+8
* Synchronous stopclk procedure for QuadSoma BhanuTej2017-08-168-82/+141
* p9_sbe_lpc_init: Fix LPC bus LRESET for DD2Joachim Fenkes2017-08-162-64/+111
* Use PHB target in p9_phb_check_quiesceSachin Gupta2017-08-141-74/+15
* Halt on zero instruction/load/store addressAdam Hale2017-08-112-2/+9
* Update p9_sbe_load_bootloader Hwp to receive the addr-key stash-2Raja Das2017-08-114-1/+50
* p9_sbe_common -- update TP LFIR to match RAS XML v95Joe McGill2017-08-101-1/+1
* Fakering and NO_DE_SWIZZLE can not go together.Sunil Kumar2017-08-091-0/+9
* Adding p9 security blacklist and whitelist filespashabk-in2017-08-081-0/+824
* Centaur istep 11 supportThi Tran2017-08-082-0/+295
* Modified gen_accessors script for greater supportAndre Marin2017-08-082-0/+19
* Level 3: For various PM HWPSangeetha T S2017-08-081-0/+1
* PM: Level3 Special Wakeup Hardware ProcedurePrem Shanker Jha2017-08-081-0/+45
* L3 Update - p9_ram_core HWPsThi Tran2017-08-083-85/+162
* L3 Update - p9_thread_control HWPThi Tran2017-08-073-275/+241
* Characterization Default ImageAdam Hale2017-08-071-2/+4
* PSTATE: PGPE_Flags-ATTR_PGPE_HCODE_FUNCTION_ENABLE FixRahul Batra2017-08-071-2/+1
* L3 update -- p9_sbe_load_bootloaderJoe McGill2017-08-074-365/+575
* B1814616 - hwsvd sig:11 core dump on zzfp247Richard J. Knight2017-08-021-1/+8
* Removed GPE halt workaround from p9_pm_check_quiesceSachin Gupta2017-08-021-21/+0
* Enabled p9_suspend_powman.CSachin Gupta2017-08-021-0/+1
* Use DD1 SW reset for XIVE unit until we get HW reset working in DD2crgeddes2017-07-313-179/+216
* p9.int.scom.initfile -- mask SUE FIR for Nimbus DD2Joe McGill2017-07-281-0/+17
* Add additional dials to risklevelNick Klazynski2017-07-281-0/+17
* p9.obus.pll.scan.initfile -- adjust Nimbus DD2 POR to 25gbsJoe McGill2017-07-281-2/+23
* p9_sbe_chiplet_pll_initf: Level 3Joachim Fenkes2017-07-263-3/+7
* p9_sbe_npll_setup: Level 3Joachim Fenkes2017-07-263-5/+61
* p9_sbe_npll_initf: Level 3Joachim Fenkes2017-07-263-4/+8
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