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* Fix to skip Osc check in sim onlySoma BhanuTej2017-11-021-57/+76
| | | | | | | | | | | | | | Change-Id: Ie7d72d588764e87050b1eded25cc8247b3e99210 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48877 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48880 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Disable core hang busterGreg Still2017-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | - Make default attribute control be DISABLED Change-Id: I77bab151700247f7ea1ab6e77529db2bb5681fcb CQ: SW406324 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48925 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48929 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Make plat init attributes non-writableSantosh Puranik2017-10-274-311/+8
| | | | | | | | | | | | | | | | | Change-Id: I382948a4083293e4ecc42a9759559a060444f5f0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34997 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35043 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* p9_sbe_check_quiesce -- dont attempt PHB DMA quiesce if ETU is already in resetJoe McGill2017-10-271-16/+20
| | | | | | | | | | | | | | | Change-Id: I32c2e2f1d2f4793a8ae42561a74d9ff3abdfa897 CQ: SW403955 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48805 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Ricardo Mata <ricmata@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48811 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Turning on NCU tlbie pacing by defaultLuke C. Murray2017-10-272-0/+51
| | | | | | | | | | | | | | | | Change-Id: I954651af59c18401a9bd5f389f86b8faf799edbd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48817 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48821 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cleanup security listspashabk-in2017-10-261-16/+0
| | | | | | | | | | | | | | | | Remove all the TODO registers from security list Change-Id: Ic0d5020a8dd83a5a0971eb0f6048200d408ddd61 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48799 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48803 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* osclite status check in clock_test2Anusha Reddy Rangareddygari2017-10-261-10/+28
| | | | | | | | | | | | | | | | | checking bits based on pci osc scenarios Change-Id: Ida0b6d97cffc1bc43d32dda1f3bdb611e26d56bf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48485 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48491 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Need to clear OCB3 errors before a PBA operationThi Tran2017-10-261-2/+5
| | | | | | | | | | | | | | | Change-Id: Iaa7246b82bc490222162ef74011db78bc8631e23 CQ:SW405593 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48647 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48649 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone UpdateAnusha Reddy Rangareddygari2017-10-243-28/+119
| | | | | | | | | | | | | | | | | * IOF0 pll initf for Axone * Clock mux settings Change-Id: I1c6350bca42fc11e8e2a93f4134ea5db76daf79e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48278 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48282 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-241-1/+1
| | | | | | | | | | | | | | | | | | | update the metadata to reflect that HWPs are product ready (HWP Level: 3) Change-Id: I7199693614997bef5d5b5c9373e20c6c44a05a1a Original-Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48503 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_setup_clock_term updatesAnusha Reddy Rangareddygari2017-10-241-3/+5
| | | | | | | | | | | | | | | Using pci_clk_req enum to set osc0 and osc1 configurations Change-Id: Ie4a45f121e9c5ecb2e4883332ac948d80ab6a6cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44218 Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48502 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove registers with TODO from BL/WL csvspashabk-in2017-10-231-83/+0
| | | | | | | | | | | | | | | | Removed all the registers with TODO so that they can be updated by the respective teams as and when they encounter it Change-Id: I2a74f2712eb22d7d3e3ee9101daf7ff626b791e3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48436 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48438 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-10-231-1/+4
| | | | | | | | | | | | | | | | | for osc switch settings Change-Id: I8279e5f96b79274685ff3bbee4f1eb4d941cfa43 Original-Change-Id: I9e762d2c4b552e84a3a2cc48ec0d9d75732b07cf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41676 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48501 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 HWP for p9_setup_clock_termAnusha Reddy Rangareddygari2017-10-231-13/+36
| | | | | | | | | | | | | | | | Also included wrap files and makefiles Change-Id: I228028a5af319ebda4343e5cf39b3f2618162470 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23474 Tested-by: Jenkins Server Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: Parvathi Rachakonda Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48500 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2017-10-231-0/+62
| | | | | | | | | | | | | Change-Id: Ibcd2d49f00e6c3488fcbde0d80adf0bdc00b2a97 Original-Change-Id: I3ea0eec08ce479057277524021bfce540d7b63ca Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17755 Reviewed-by: Brian Silver <bsilver@us.ibm.com> Tested-by: Brian Silver <bsilver@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48499 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
* Additional checks to p9_extract_sbe_rcSoma BhanuTej2017-10-231-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | - To detect NDD1 or other chip for seeprom & otp addr upd - pibmem program exception - otprom program exception - Use sbe_cs bit to identify the state of pk loader - Adding CBS_STATUS_REGISTERS,ROOT_CTRL_REGISTERS in xml - Using ifndef __HOSTBOOT_MODULE while read MBOX registers - Update all Non-Secure mode RC names Change-Id: Ic764bbda94d9beb023aa1861cb143bf05b8ff06a RTC: 174954 CQ: SW404908 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41738 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42614 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* VDM: p9_pstate_parameter_block check for VDM Large threshold < -32mVGreg Still2017-10-151-1/+19
| | | | | | | | | | | | | | | | | | | | | | | - filters out old VPD parts (Nim 2.01) to just disable VDM instead of using bad jump values - check only applies for #W with version < 3 to allow for future proofing - Added error log suppression EC attribute for < Nimbus 2.1. Change-Id: Id91fc1f816b5a3da08730feb726a246d802429db CQ: SW404757 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47964 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Francesco A. Campisano <campisan@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Francesco A. Campisano <campisan@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48047 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PLL updates for filter BG, BW including OBUS tank coreqsJoe McGill2017-10-142-3/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9.filter.pll.scan.initfile adjust BG offset to -1 for P9n DD2.[12], P9c DD1.1 apply BW updates to P9n DD2.2, P9c DD1.[01] p9.obus.pll.scan.initfile apply BW updates to P9n DD2.2, P9c DD1.[01] with tests 108, 109, 110 p9_frequency_buckets: default Cumulus OBUS bucket 0 to 25.625gbs chip_ec_attributes.xml add feature attributes for BG, BW controls Change-Id: I5e06da5267db70bb1d6e6eae066611577d32ac7b CQ: HW423532 CQ: HW423535 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48267 Reviewed-by: Ann C. Wu <annchen@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48269 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use compiler definition for size_tSachin Gupta2017-10-131-2/+2
| | | | | | | | | | | | | | | | | We get multiple definition issues if we include ppe42_string.h as stddef.h also has defined size_t Change-Id: I44ec000db4df176f36d185842dd8057b2b03e28d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48101 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48123 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating L2 re-request jitter settings for CumulusLuke C. Murray2017-10-121-0/+17
| | | | | | | | | | | | | | | | | | Change-Id: I5475bdfebc117ed16e8de09443a8d263742e1d2d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48197 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48203 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Workaround for HW421347 Scandalous PieLuke C. Murray2017-10-121-0/+25
| | | | | | | | | | | | | | | | | | | | | | This was the core hang going into re-config because of L3pref unfairness in the L2 CIU between cores. Change-Id: Ic58c2e0a92e4aef0a1076b09bbdd65e9ba17421a CQ: HW421347 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48035 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48038 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW415883 applies to NDD2.1, Add JellyVector WAT, add HW422495, add HW421831Nick Klazynski2017-10-122-15/+16
| | | | | | | | | | | | | | | | | | - WAT replaces original workaround for HW419818; two dials removed Change-Id: I540aead6556278a1da3774eba2d96cb685c4e3c1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47181 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47958 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Share common code between p9_l2_flush and p9_l2err_linedeleteThi Tran2017-10-113-131/+161
| | | | | | | | | | | | | | | | | Change-Id: I547078b1e0fc7adec767402faf5e64e4b4390bc9 RTC: 178071 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46359 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46385 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_chiplet_reset: Set VITL_AL flag for MC chipletsJoachim Fenkes2017-10-092-0/+6
| | | | | | | | | | | | | | | | | | | | | There is a phase sync signal between the Nest and MC chiplets that is only needed for combined synchronous LBIST of the inter-chiplet interface, but can disrupt scanning in async MC operation. So it should be masked in normal operation by setting the VITL_AL flag in NET_CTRL0. Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251 CQ: HW422475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: LENNARD G. STREAT <lstreat@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48057 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_enable_ridi -- restore old behavior for cache contained mode supportJoe McGill2017-10-061-1/+24
| | | | | | | | | | | | | | | | Enable TP RIDI in this step for Cronus only, in cache contained mode Change-Id: I58635087fe6a924db32ada48a34f5df65fc44aa7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47000 Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47006 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HWSV Dump component put scom registersspashabk-in2017-10-061-0/+46
| | | | | | | | | | | | | putscom registers used in dump Change-Id: I57fdb15869dea17ba4067b569958295c781b7c18 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46262 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47114
* HWSV whitelist registers additionspashabk-in2017-10-051-42/+62
| | | | | | | | | | | | | | | Special wakeup registers Change-Id: I66f433fb118b53c8db6f99f5d6c2f409aeb4fdc3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46739 Reviewed-by: Srikantha S. Meesala <srikantha@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46773 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* New PPE state dump utilityAmit Kumar2017-10-051-0/+37
| | | | | | | | | | | | | | - Added support for CME - Fixed Minor SPR issue - Added -dump/force_halt switches Change-Id: I27216eb0e09e9b71614b78757734a16813433583 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23926 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48026 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM (Cronus): Add processor id for errors from p9_activate_stop15_coresGreg Still2017-10-051-0/+20
| | | | | | | | | | | | | | | | | | | | | | - reformatted error output for readability - removed FAPI_ASSERT FFDC as these are not useful in Cronus; moved the FFDC to printfs before the ASSERT - Added isHalted() to ppe_utils - added SSH and better SGPE oriented register FFDC - removed extra setBit to core_sb buffer Change-Id: Iea97073305609845c51d5106200e3b0fbfbde0bf Original-Change-Id: Ie23f294b843b15a78b8d3ee036310631c0595904 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44758 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48012 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: PPE State tool fixes.Prem Shanker Jha2017-10-051-131/+41
| | | | | | | | | | | | | | | | | | | Commit addresses various issues with PPE State tool: - exports various functions to through header file - documentation and variable update. - removes inclusion of p9_ppe_utils.C in other source files. - makefile updates Change-Id: I6f18dd9f3987700a76be4258f1e53ae20248c32e Original-Change-Id: I0d5fc178cf04c23add5df00b59b9d6243695de99 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42467 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48011 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert PLL unlock commits of 45102 and 46563Yue Du2017-10-053-21/+3
| | | | | | | | | | | | | | Change-Id: I27f7c75d73881a54152a77c7ab2c8b49be19adb7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47148 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47162 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SIBRC detailsAshish2017-10-051-142/+65
| | | | | | | | | | | | | Change-Id: I8cb5e51ea84e59496fdf85fb5c815c3378045f5e Original-Change-Id: I8159352751dd039f44e851315bf2b9d4cb1ab5fb Cange-Id: I2b728046ef7b898666d3f1f0076e387f2d937f5b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32173 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48010 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* code bug: single step was not restoring dbcrAshish2017-10-051-1/+2
| | | | | | | | | Change-Id: I8980432fb6bfa2c41e709a1a5a0c111a151753f7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31888 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48009 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_ppe_commands: add -step_trap supportGreg Still2017-10-051-1/+210
| | | | | | | | | | | | Change-Id: I195c9f06180bc90368dd909f65cba0d7fbdad43f Original-Change-Id: I734f2cafae2d6cb67b909459b80266052a988542 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31451 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48008 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_ppe_commands : Enhanced single stepAshish2017-10-051-35/+178
| | | | | | | | | | | Change-Id: I2c715769f4eab2be39497296842e04cbd7d38443 Original-Change-Id: I7dfd4a1cde9147b011584a8404a3f73f2412ff24 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30086 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48007 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PPE command line controlAshish2017-10-051-0/+485
| | | | | | | | | | | Change-Id: Idaabcdd1ab3e6e919e865f364cf912f4752626e0 Original-Change-Id: I467470a2a8832dc1ada7568cd3773ee53d61cbe9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48006 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_thread_control -- remove threads_running check from sreset, start code pathsJoe McGill2017-10-042-113/+0
| | | | | | | | | | | | | | | | | | | | | After a write to DIRECT_CONTROLS, the targeted thread will start executing instructions, which may include STOP. Future polling of the RAS_STATUS register is not guaranteed to satisfy the threads_running check (by the time RAS_STATUS is polled the thread may be idle again) Change-Id: Ie3628149cef5089fb635256df5a25f08dbd828dc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47069 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47076 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update default case in set_sbe_errorRichard J. Knight2017-10-041-0/+1
| | | | | | | | | | | | | | | | | | -Capture the ERRVAL as well as the FFDC buffer Change-Id: I7d15d3215c85128e98b188cf316a4e763448c074 RTC:169625 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45344 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: ARAVIND T. NAIR <aravindnair@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45349 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* {nest,cache}_pll_setup: Properly clear PLL unlock indicationJoachim Fenkes2017-10-042-3/+9
| | | | | | | | | | | | | | | | | | | | p9_sbe_npll_setup used a bad target to clear the PLL unlock indication (luckily the misguided writes hit benign registers) p9_hcd_cache_dpll_setup didn't clear the unlock indicator at all CMVC-Prereq: 1035048 Change-Id: Ia77e8f168e00eba9effb9b3cf0bbb7df2e814749 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45100 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45102 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM (Cronus): Add processor id for errors from p9_activate_stop15_coresGreg Still2017-10-041-0/+13
| | | | | | | | | | | | | | | | | | | | | - reformatted error output for readability - removed FAPI_ASSERT FFDC as these are not useful in Cronus; moved the FFDC to printfs before the ASSERT - Added isHalted() to ppe_utils - added SSH and better SGPE oriented register FFDC - removed extra setBit to core_sb buffer Change-Id: Ie23f294b843b15a78b8d3ee036310631c0595904 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44758 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47138 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: PPE State tool fixes.Prem Shanker Jha2017-10-041-15/+304
| | | | | | | | | | | | | | | | | | Commit addresses various issues with PPE State tool: - exports various functions to through header file - documentation and variable update. - removes inclusion of p9_ppe_utils.C in other source files. - makefile updates Change-Id: I0d5fc178cf04c23add5df00b59b9d6243695de99 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42467 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47137 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SIBRC detailsAshish2017-10-041-8/+77
| | | | | | | | | | | | Change-Id: I8159352751dd039f44e851315bf2b9d4cb1ab5fb Cange-Id: I2b728046ef7b898666d3f1f0076e387f2d937f5b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32173 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47136 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_ppe_commands: add -step_trap supportGreg Still2017-10-041-6/+6
| | | | | | | | | | | Change-Id: I734f2cafae2d6cb67b909459b80266052a988542 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31451 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: ASHISH A. MORE <ashish.more@in.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47135 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_ppe_commands : Enhanced single stepAshish2017-10-041-10/+25
| | | | | | | | | | Change-Id: I7dfd4a1cde9147b011584a8404a3f73f2412ff24 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30086 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47134 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PPE command line controlAshish2017-10-041-0/+150
| | | | | | | | | | Change-Id: I467470a2a8832dc1ada7568cd3773ee53d61cbe9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28719 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47133 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove HB incorrect setting of ATTR_DD1_SLOW_PCI_REF_CLOCKThi Tran2017-10-041-1/+1
| | | | | | | | | | | | | | | | | Change-Id: I306fbb6ce0a128f61fc58aa4ed10ac53470eeb90 CQ:SW403259 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46988 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47067 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-0470-103/+103
| | | | | | | | | | | | | | | | | | | update the metadata to reflect that HWPs are product ready (HWP Level: 3) Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46791 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* TOR Magic header supportClaus Michael Olsen2017-10-044-302/+425
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | HW-Image-Coreq=Yes SBE-Image-Coreq=No (SBE image is back compatible) This commit adds an 12-byte header to all TOR ring sections: - for improved self-containment of TOR ring sections incl stand-alone ring sections like .overrides which, currently, has no meaningful size info associated with it in the PNOR, - to support a more data-driven implementation of TOR API, - to eliminate the current usage of XIP_MAGIC ids to inform the TOR APIs which ring section they are dealing with, and - to improve debugging binary ring sections. The TOR header expands on the current TorNumDdLevels field in the HW ring section and is added to all other ring sections as well, e.g. for the SBE and OVRD ring sections. Most importantly, the TOR header adds the TOR magic number which is unique for each possible TOR ring section. Also, of quite practical importance, a size field has been added so that the size of a true standalone section like .overrides can be extracted (since its size in PNOR is not indicative of its size). Further, to support the use of ddLevel and chipType in the TOR header fields, these two data points need to be always supplied whenever calling ring_apply. Thus, updates have been made to the ring_apply.mk file as well as the override .pl script. While making these changes, we also decided to change the --type arg to the --bOverrides arg to make the arguments being passed less confusing in view of the Centaur commit that's coming and its demands to make codes less data dependent, incl make and script files which should simply inform the functional intent of the "user". The user shouldn't presume it knows about which specific type of ring section needs to be produced. Further, the DD level block struct has been increased from 8B to 12B to avoid the unnecessarily complex merging of the ddLevel and offset into the same 4B field. It's included in this commit since this is also going to break the lab and because the required code changes are in the same places where the code changes needed for the TOR header are. Further, xip_tool has been updated to support the new TOR header so that it can be called by supplying a standalone ring section, such as overrides.bin. Various changes have been made in xip_tool's dissect section to support overrides as well. This code uses many of the code changes in 33778 except changes to p9_tor.C|H are at a bare minimum focusing on the functional changes and keeping any cleanups to a minimum changing only some variable names associated with the functional changes for improved readability of the code. CMVC-Prereq: 1034144 CMVC-Prereq: 1035575 Change-Id: I29ba8905ac55dad5c10878a94fb94468e5580ea0 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35372 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37993 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add workarounds for HW421426 and HW422629, Swap IMCs aroundNick Klazynski2017-10-041-0/+41
| | | | | | | | | | | | | | | | | | | IMC6 and IMC7 cannot be controled by software; Linux team wants the entry currently in IMC6 configurable, so it must be switched around. Change-Id: Iab7779b620f82a654055fb566eed09f6608314fd Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47014 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47023 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove functionality from tp enable ridi and move it to nest enabled ridiChristian Geddes2017-10-023-26/+47
| | | | | | | | | | | | | | | | | | | Previously, we were enabled TP RIDI before we did a bunch of scans which touch LPC logic. This was causing LPC logic to get messed up because once TP ridi is enabled LPC traffic is flowing. To get around this, we are moving the enablement of the TP RIDI to after the scans of the LPC logic so that the LPC logic wont get messed with Change-Id: I6244fdf1314a21d9c76519bde3905287c7870b26 CQ: SW396004 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46941 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46966 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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