| Commit message (Collapse) | Author | Age | Files | Lines |
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Change-Id: Ic85a9ef789f9bc337eae62bf6814287bf2845890
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52068
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Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52074
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I7a2bc6abf4a2bad1ed6c18147bab67f30f6574f4
Backport: release-fips910
CQ: SW413942
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52221
Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52225
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
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Change-Id: I488c09c98383c287b9812c59e92cf9647ac9c042
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51517
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Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
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Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51524
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I4cc1e50a848d627f0ec3917bb8ebd39f20dc9466
CQ: HW420338
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51719
Reviewed-by: YUE DU <daviddu@us.ibm.com>
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52219
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I73d38d6029a5b84590d1081855e12c145a535869
CQ: SW413192
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51338
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51345
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ief523bd33a34a6a96f61664f6ab3545d9dc15d98
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52050
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52121
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Within the PK interrupt vector, if you have a function call from
one function to another, it needs branch link instruction, but
since the BL is already being used to jump from software context
to the PK Vectored Interrupt context, the function call from within
will corrupt the Link register.
For interrupts like data_storage, instruction_storage,
alignment_exception and program_exception, the save-off will
capture the LR registers to indicate which interrupt was getting
executed when halt happened. For Machine check handler, LR won't be
valid.
Change-Id: Iee17b37acd438c7bee2c956cac2de3ce64d04441
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51587
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Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51588
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Change-Id: I0d0aebc925c963a32e2cf2266e833df84a799235
CQ: HW409194
CQ: HW407065
CQ: HW419541
CQ: HW430944
CQ: HW417829
CQ: HW422533
CQ: HW414249
CQ: HW432749
CQ: HW414146
CQ: HW433125
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51677
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51685
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I5435bef91381ade76a1439a842fa90b86e17aab3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51599
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Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
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Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51604
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Bit mask of group IDs which will be present in the fully configured
CEC configuration.
Change-Id: I43b06e856d2b285bb919025926b914d3ec4de451
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51692
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51701
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: If2916c99b37c4ce56ad1cf6f6957d67497fac5ab
CQ: SW412668
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51394
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Iee18d460dc99de59eb0b1f8891dad1e8698e3208
CQ:HW430944
CQ:HW432070
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51370
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This update propagates the extracted EC level in xip_customize
through to the TOR API via the call to tor_get_single_ring(). The
TOR API has been updated to verify that the requested DD level
matches matches the DD level in the TOR header of the supplied
ring section which, in the case of xip_customize, is an .overlays
ring section.
Key_Cronus_Test=XIP_REGRESS
Change-Id: Ic087c269306acc0afcb8c759fe68eac63ae93d29
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Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I6c64841173f036c4898c199ef1615046a3974dcc
CQ: HW422471
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48525
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Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50964
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- IMC6 changed to implement special nop
- IMC7 serializes bcctr for NDD2.2/CDD1.1
- mttrig2 moved to mttrig0
- mttrig2 now causes an L1 flush on NDD2.2/CDD1.1
- Force private L1D
- branch hint bits always honored
- enable new TM mode for NDD2.2
Change-Id: I3b724f6d742b9ba321ea1abbfa6bbc7d5482b8ed
CQ: HW430733
CQ: SW410726
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50872
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51025
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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centaur.mbs.scan.initfile
Remove static application of read data delay disables
Centaur will now flush to read data delay enabled
cen_initf
Add block to re-rotate tcn_mbs_func and:
- fix existing spy parity errors
- apply read data delay disables,
executed only when attached chip is Cumulus DD1.0
Change-Id: I10279decbbf27df911a94ce27d11b4d2e30b6e5f
RTC: 138785
CQ: HW419021
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50720
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50735
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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That delay was always compiled into the procedure and we tested with
it, so let's make it permanent.
Change-Id: If8a5c6fbf4bd8b42e37656f66ced96604813485b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48748
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Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48754
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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cen_ringId.CH
cen_ring_id.h
add entries to hold multiple PLL rings, 8 in total
cen_initf.C
cen_pll_initf.C
cen_pll_initf_errors.xml
replace invocation of generated initfile HWP with putRing API calls
(rings to be scanned gleamed from p8 cen assembly source)
select correct PLL ring image based on NEST,MEM frequency
cen_bucketX.txt
define frequency points for each PLL bucket
1 = 2000 MHz NEST, 1066 MHz MEM
2 = 2000 MHz NEST, 1333 MHz MEM
3 = 2000 MHz NEST, 1600 MHz MEM
4 = 2000 MHz NEST, 1866 MHz MEM
5 = 2400 MHz NEST, 1066 MHz MEM
6 = 2400 MHz NEST, 1333 MHz MEM
7 = 2400 MHz NEST, 1600 MHz MEM
8 = 2400 MHz NEST, 1866 MHz MEM
ipl_base.txt
ipl_risk.txt
remove frequency attributes from base attribute files
scan_procedures.mk
add rules to generate PLL buckets
Change-Id: I8aee5e82337800ea9afe9a9af12d8d34f6e1e01e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50475
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Reviewed-by: Richard J. Knight <rjknight@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50478
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I1c93a9b505e6656ea9bda20a7fac363e037a3d73
CQ: HW430546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50832
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Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com>
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Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50979
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I0068d797ad4a82216e440f701c5182ad95584a15
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51503
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51504
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This commit is the first part of 49692, which is splitted in
order to have SBE platform proceed with code supports.
Change-Id: I1f491cac6cfef8476487217067d69d4551de1228
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51048
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51049
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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to support WIN32 for manu team.
Also,
- various updates to dd_container error handling,
- improved DD support query checking.
Change-Id: I2eab02732b3852698d8ffba5eed16a5e0bb37faa
Original-Change-Id: I706e56258894c3453cf01aa1a637fe888af1db00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46596
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51558
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCI oscillator checking code in proc_clock_test2 always checked both
osc error bits, which fails on a Cumulus system with only a single PCI
refclock active. Modify it to check osc error bits depending on which
oscillators have been configured in the osclite config.
Change-Id: I8c5ee38f8bc718dbb8eab59139a19800bb3a9f6f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51723
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Martin Padeffke <padeffke@de.ibm.com>
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51796
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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chip_ec_attributes.xml
add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need
MCD disable for HW423589 (applied to Nimbus EC20 and 22+)
p9.cxa.scom.initfile
p9.int.scom.initfile
p9.l2.scan.initfile
p9.l3.scan.initfile
p9.mmu.scom.initfile
p9.ncu.scan.initfile
p9.npu.scom.initfile
p9.nx.scom.initfile
p9.trace.scan.initfile
p9.vas.scom.initfile
p9_pcie_config.C
set unit scope disable dials
p9_sbe_scominit.C
p9_pm_pba_init.C
set PBA unit scope disable dial
p9_pm_set_homer_bar.C
change PBA0 default command scope from GROUP to NODAL
p9.fbc.ab_hp.scom.initfile
disable group master setup
p9_setup_bars.C
p9_setup_bars_defs.H
skip MCD setup for HW423589_OPTION1
cmvc-prereq: 1043014
Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2
CQ: HW423589
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I05b7b14e8ce7fdb61be1a5e6ccefc2e49beeeb4f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51236
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com>
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Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51239
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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Change-Id: If9ce191a8d09ccf4cd46fd9daabb26bfe8012fef
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45780
Reviewed-by: ARAVIND T. NAIR <aravindnair@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Srikantha S. Meesala <srikantha@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51522
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4245ba11c525e8406cf24554b2c0194c8023c13d
Original-Change-Id: I4c9d8cb28d4ae6a8b21c87ebaad07c1fd7163b85
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/39588
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51557
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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I inserted P9A before CT_CEN for purely estaetic reasons. Since
the current Centaur image in EKB isn't being used yet, this
should be safe (as otherwise there would be a co-req
situation).
Change-Id: Ia5ef9950644eacea3fdc28a0195502bdcae44327
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50812
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50962
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I8cf51a4e044c70871c5f74a5d3a6ecfe64dafd47
CQ: SW411044
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50779
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50992
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Nimbus DD2.0 disable will go into op910 only (for Boston Coral)
but not into master
Change-Id: I28376316be3e6700af97df83a02c48e46d715dec
CQ: HW415945
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50445
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50453
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCIe timeout have increased to 66-100ms, so we need to double
the NCU master timeouts to be above these timeouts. This has a
chain effect causing the L2/L3 master timeouts to increase which
causes the tlbie snooper to increase which causes the tlbie master
to increase.
This would also ususally cause the core timeout to increas, but
the core is already at around 13 seconds, so there is headroom
there.
Change-Id: I5930076151267a9bfa66e24edef0985c165db0b7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50582
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Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50602
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Upon PGPE Halt
1) SGPE performs STOP Recovery Trigger to set
a malfunction alert and removes PGPE IPCs
from wake-up decisions.
2) CME is interrupted by QPPM OCC Heartbeat
Lost that PGPE stopped updating
Upon SGPE Halt
1) PGPE moves to Psafe
2) PGPE performs STOP Recovery Trigger to set
a malfunction alert.
This commit also includes SGPE Panic Code
Cleanup such as debug halt support.
However PGPE Panic Code Cleanup is dealt in
a different commit
Key_Cronus_Test=PM_REGRESS
Change-Id: I893aa1ef21d2f684722b8c10dbbeb92b9505c1c4
CQ: SW410252
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49275
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Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
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Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49429
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I4f59cabf7439590ac736e6f64e35acf11e6c5aa9
CQ: SW402715
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46944
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46950
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Key_Cronus_Test=PM_REGRESS
Change-Id: I823b350ffe1e07108fbadd4b0456c7188839932f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46480
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48106
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This attribute was both platInit and writable, that should not
be the case. After talking w/ HW guys
Change-Id: I9d12581cf2772715693e8b0a8dc539aeff87cc85
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50908
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50912
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- In order to set VDN voltages across the Master->Slave FSI links from Hostboot
prior to XBus training, the AVSBus bridge registers have to be accessible
through the SBE.
- While the present code uses only the AVSBus O2S "B" bridge, both A and B
bridge addresses are added so as to not be limiting in the future. The
bridges are identical and are present to allow for Firmware separation.
Change-Id: Ib702c2e49a2533deb4b2898cd533faab349ddf5c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50657
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50662
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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Change-Id: I72d3649a173fecee990c7ec1793568675be6c53d
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50831
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50837
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 41352b2d444e98639eedc06b1eb0d8da89d4adb3.
Change-Id: Ic3f2099eff3f5c942ef8fb6916e8ee78ca1a9e82
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50703
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50722
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I94211977e9eca2d26a929d59fb4d582cbcfefb61
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50746
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50750
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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Created ATTR_FREQ_PB_MHZ_POUNDV_FALLBACK to handle a few cases
where modules were created with invalid #V for the frequency we
would like to run them at. The code will use the real powerbus
frequency to find the #V bucket (no change from current behavior)
but will fall back to the new attribute if no matches are found.
Change-Id: Ie15190ac092ca797a8a51d41eece7c4cd2d0f136
CQ: SW410357
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50677
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50682
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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pervasive_attributes.xml
sbe_attributes.xml
create ATTR_FILTER_PLL_BUCKET to encapsulate BGoffset selection
p9.filter.pll.overlay.scan.initfile
generate correct BGoffset value based on ATTR_FILTER_PLL_BUCKET value
build must process 4x (ATTR values 1..4) to generate set of ring images
p9_xip_customize.C
consume AW keyword from MVPD, set ATTR_FILTER_PLL_BUCKET for HB platform
and customize into SBE image if attribute is present in image
p9_sbe_npll_initf.C
p9_sbe_npll_initf_errors.xml
re-scan perv_pll_bndy ring with selected BGoffset overlay when
ATTR_fILTER_PLL_BUCKET is non-zero
p9_sbe_chiplet_pll_initf.C
p9_sbe_chiplet_pll_initf_errors.xml
adapt to error XML updates in p9_sbe_npll_initf
Change-Id: Id09074d12e95ffc44337e32ec683056d8ec390f3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49442
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49460
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 702e418be9ace793c323710411c2ca6b4d032c58.
Change-Id: Iebbea4e980a974a10a46345262bd475e3e340771
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50800
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50802
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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As it is no longer a requirement that Spread Spectrum is enabled on all
SS PLLs in a system in unison, we're better off turning on spreading
as early as possible, so any link training runs off of a spread clock.
The only way to enable Spread Spectrum in P9 is via the TOD Timer, so
we have to set up a timer compare value of 1 and force the TOD value to
1 so that the timer is hit and the TOD's spread enable output turns on.
Change-Id: I0bcd33f17ef06beafb44ba6777d32b98d0680deb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49662
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Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49667
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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1. align data per FFDC member names
2. set the atomic lock FFDC so that errl parser works
3. collect sibling core data if in fused mode
4. do not collect ffdc on check_master_stop15 fails,
as SBE will do that upon a chip-op request
See https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49473
for FW changes
Change-Id: I9880cdd3480c84c418b662fb7174291ed7b68cdd
RTC: 179364
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50648
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Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50653
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-STOP11+WOF Fix
-STOP11+WOF+Safe Mode
Key_Cronus_Test=PM_REGRESS
Change-Id: I7aae651213174049fa4fe89d6ac92fda2478e90a
CQ: SW410652
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48989
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com>
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Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49320
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Adding CTEPERLPATH to ENV-setup
Jenkins failure CQ SW40996
Change-Id: I02a9c5f31fb0545e8f8c8cd99b528a467ae52cf8
CQ: SW409966
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45266
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Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50688
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Turning on the 64B store prediction inside the L2. This is a
performance fix.
Change-Id: I2e91747e2cf420ffa50efeb73b8876e54c89b8d6
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50531
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50542
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ibf7f3276279e99e82841d2a209230ce38081c419
CQ: HW426816
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50480
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
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Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50607
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I209bf1735b7107303bbd9009d7c99201809ba8bf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50315
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Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50337
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Our timeouts for suspend_powman were way to short. This commit
increases the timeouts by a factor of 1000. Per request from M.
Floyd on PM team.
Change-Id: I03c6e452a453979128d232c33d31ff9fd9dfbe6b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50470
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50474
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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