summaryrefslogtreecommitdiffstats
path: root/src/import/chips
Commit message (Expand)AuthorAgeFilesLines
* Set size of enum CHIPLET_TYPESachin Gupta2017-07-251-1/+1
* p9_sbe_tp_chiplet_init3: Level 3Joachim Fenkes2017-07-253-42/+76
* L3 Update - p9_l2/l3_flush.CThi Tran2017-07-246-223/+199
* Suspend HWP Halted CheckingAdam Hale2017-07-241-58/+72
* p9_sbe_tracearray: Nimbus DD2 updatesJoachim Fenkes2017-07-243-59/+154
* Removed unnecessary FFDCSachin Gupta2017-07-202-13/+1
* FAPI2 - Enable register ffdc supportRichard J. Knight2017-07-201-1/+4
* Istep4: procedures upgrade to level3Yue Du2017-07-2061-790/+842
* p9_sbe_check_master_stop15: Level 3Joachim Fenkes2017-07-204-23/+38
* Add pm_check_quiesce function to list of sbe_check_quiesce functioncrgeddes2017-07-192-0/+65
* Optimized PPE FFDC collection frameworkAmit Tendolkar2017-07-198-185/+171
* Make freq_x_mhz attribute writeablecrgeddes2017-07-191-1/+1
* PGPE: WOF Phase 2Rahul Batra2017-07-191-0/+18
* NMMU FIR, RAS XML updates for Nimbus DD2Joe McGill2017-07-191-18/+18
* updates for thread control, ramming with STOP enabledJoe McGill2017-07-192-65/+42
* chip XOR swap -- use absolute fabric group ID to form bootloader load addressJoe McGill2017-07-194-11/+25
* Dumy commit to work-around auto-mirror issue from 38781Amit Tendolkar2017-07-181-0/+1
* Have SBE set PSSCR in fused core modeDean Sanner2017-07-171-7/+18
* suspend hwp changes and additional ffdcAdam Hale2017-07-172-120/+99
* p9_query_cache_access_state L2CHRISTINA L. GRAVES2017-07-171-0/+88
* pm suspend methodology and ipc updateAdam Hale2017-07-171-1/+2
* PM: Clear CPMMR PPM_WRITE_DISABLE for suspendBrian Vanderpool2017-07-171-0/+11
* WOF: HWP support for advanced function enablementGreg Still2017-07-171-67/+68
* PSTATE: CME refactoring and cleanupRahul Batra2017-07-171-56/+37
* Pstates/Lab: Add unblocking for DPLL/VRM/VDM/Resclk to pm_suspendBrian Vanderpool2017-07-171-72/+107
* WOF: VRM timing, WOF and VDM enblement attributes additionsPrasad Bg Ranganath2017-07-171-2/+10
* PM: Updated QPMR and SGPE Header with 24x7 offset and length.Prem Shanker Jha2017-07-171-4/+4
* STOP: block wakeup (+ block entry since patch 15)Yue Du2017-07-171-4/+29
* PM: Added support for PGPE Boot/PGPE integrationPrem Shanker Jha2017-07-171-0/+31
* OCC Flags/OCC Scratch UpdatesRahul Batra2017-07-171-0/+205
* OCC Flags/OCC Scratch UpdatesRahul Batra2017-07-171-15/+13
* L2 p9_suspend_powmanCHRISTINA L. GRAVES2017-07-173-0/+285
* Enable skipping sbefifo reset during p9_start_cbsMatt K. Light2017-07-171-0/+10
* GPTR/Overlays stage-1b support in xip_customizeSumit Kumar2017-07-176-63/+15
* xip_customize: GPTR/overlays stage 1 supportClaus Michael Olsen2017-07-172-5/+19
* Add WA for HW415988Nick Klazynski2017-07-141-0/+19
* PM: Delete deprecated attributesGreg Still2017-07-145-110/+425
* Create dmi.pll.scan.initfileBen Gass2017-07-147-8/+126
* HCODE: DD21 makefile changes for CME,PGPE and SGPEPrasad Bg Ranganath2017-07-143-11/+20
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-07-141-46/+15
* HW414700 checkstop on UEs and disable core ECC counterLuke C. Murray2017-07-133-2/+36
* Add PERV chiplet to MCGR 0Anusha Reddy Rangareddygari2017-07-131-0/+5
* Change DD2 #if statements to correct SBE conventioncrgeddes2017-07-131-19/+21
* Quad FIR updates for Nimbus DD2, MPIPLLuke C. Murray2017-07-121-2/+2
* DD2 updated scan overrides, Cumulus DD1 initfile updatesdchowe2017-07-121-0/+25
* mc_pll_bucket attributeAnusha Reddy Rangareddygari2017-07-123-0/+24
* Disabling LVext for all P9 partsLuke C. Murray2017-07-121-18/+0
* dcc skew adjust procedure updateAnusha Reddy Rangareddygari2017-07-123-229/+281
* p9.pci.scan.initfile -- initial releaseJoe McGill2017-07-121-0/+16
* p9.npu.scom.initfile -- Nimbus DD2 updatesJoe McGill2017-07-121-18/+0
OpenPOWER on IntegriCloud