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* Add RL0/RL1 support for CDD1.2Nick Klazynski2018-06-241-8/+31
| | | | | | | | | | | | | | Change-Id: I21d861481b9909ea024934e8b5830521d407c9a7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60873 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60884 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* correctly propogate bad return code from p9_adu_coherent_status_checkJoe McGill2018-06-182-9/+17
| | | | | | | | | | | | | | | | | | | p9_adu_access.C p9_adu_setup.C save current_err to local return code object at start of exit path, and return the saved value at exit (prior code was clobbering current_err by call to cleanup routines) Change-Id: I2f247ba2e93c673b3581e3ebe1504d4f05cb3a24 CQ: SW434090 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60607 Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60618 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support new field for greylistSachin Gupta2018-06-181-980/+980
| | | | | | | | | | | | | | | | New field Bit Mask has been added. If this field is present, only putScomUnderMask is allowed. Mask in putScomUnderMask should be either same or superset of Bit Mask in greylist. Change-Id: Ibc0ff61918f15ab0193e7cbe55080b7573d11f2e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60683 Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60689 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR 37 only when MF oscswitch redundancy enabledJoe McGill2018-06-182-3/+13
| | | | | | | | | | | | | | Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adapt p9_sbe_check_master_stop15 for bad path on non-SBE platforms for fleetwoodAmit Tendolkar2018-06-173-29/+107
| | | | | | | | | | | | | | | | | | | | | | | | | | 1. On PENDING/INVALID_STATE RCs, need some FFDC and service actions on FSP using regular FAPI mechanisms like FAPI_ASSERT and register ffdc colletion 2. SBE still uses existing mechanism and restrictions - optimized for space a. no fapi error xml based callbacks b. no fapi error xml based register ffdc collection c. max local ffdc members < 20 d. depends on p9_collect_deadman_ffdc for FFDC with RC TIMEOUT 3. Compile out extra code on SBE builds Change-Id: Id35f9a7dbfc7e423bd7cf0846f493a8270a48cd6 CQ: SW430391 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60320 Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60391 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* shift OBUS FIR programming inits for secure bootJoe McGill2018-06-172-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_scominit: unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE platform only) p9_fab_iovalid: conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14 (will handle unmasking here when insecure -- Cronus or old SBE images) p9_obus_extfir_setup: new HWP for HB to call, mask OBUS EXTFIR bits for unused busses Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361
* Add TOD delay register in whitelistSachin Gupta2018-06-141-0/+1
| | | | | | | | | | | | Change-Id: I19845b7376170935b3f5715e01c7f0381f4b4f60 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60543 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60547 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_security_white_black_list -- add whitelist entries for OBUS FBC link bringupJoe McGill2018-06-141-0/+20
| | | | | | | | | | | Change-Id: I751a3cf36abf355f5b53ab29a64b763a7ffaab2b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60238 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60249
* Update whitelist for p9_block_wakeup_intrSachin Gupta2018-06-141-0/+3
| | | | | | | | | | | | | Change-Id: I9dce4fd043a05cce88a08940ea7131f255c3eb99 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60369 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60373 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update p9n_23 engd with n23_e9108_3_tp105_ec408_soa_sc_u138_01 dataBen Gass2018-06-131-1/+15
| | | | | | | | | | | | | | Change-Id: Ib586128b6152c2afb300b984c115d0d9fa8e0e15 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59588 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59596 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_common -- mark TP LFIR bit 37 as recoverableJoe McGill2018-06-111-1/+1
| | | | | | | | | | | | | | | | | | | TP LFIR 37 is meant to be marked recoverable for Cumulus 60118 unmasked the bit, but the default action register settings are programmed to trigger a checkstop. This adjust the action1 register default to recoverable. Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60261 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add A bus initialisation registersSachin Gupta2018-06-081-0/+1
| | | | | | | | | | | | | | | | | There are around unique 200 indirect registers used by A bus procedures. As in indirect registers, we only check lower 32 bits adding one register only. All other registers differ in upper 32 bits. Change-Id: Ia6c629f33b8ed96a70c835287ed1e1f8a70f2232 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60199 Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60203 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR bit 37 for CumulusJoe McGill2018-06-083-0/+37
| | | | | | | | | | | | | | | Change-Id: Id216f65d5c240d88c4db62e374c9f3278d623fbb CQ: SW432374 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60118 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60125 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update some defaults for AVSBUS attributesDan Crowell2018-06-081-20/+8
| | | | | | | | | | | | | | | | | | Added explicit defaults for AVSBUS attributes Deleted ATTR_VCS_ID_RAIL Change-Id: I8fdcd049d209af34dfa6ef354a4452641b9ee345 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59461 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59472 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM:Remove deprecated attributesPrasad Bg Ranganath2018-06-061-14/+0
| | | | | | | | | | | | | | | RTC:173736 Change-Id: I49d8506f97f0fb61c1117fd57fe1fa302ad44b04 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59837 Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59840 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Blacklist violation error due to 0x04011821 SCOMSrikantha Meesala2018-06-061-0/+1
| | | | | | | | | | | | | | Change-Id: I8290029aefeb381487fbb7206f94a89a91e790a7 CQ: SW430223 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59377 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59380 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* mask core SPATTN bit used for core checkstop handshakeJoe McGill2018-06-051-0/+2
| | | | | | | | | | | | | | Change-Id: I9c0a7224c3880ab40bb9111d8f66449912029e2f CQ: SW431474 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59707 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59713 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* support IO reconfig loop for OBUS DL link training failuresJoe McGill2018-06-042-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | - p9c DD1.1+ only, DD1.0 not supported - FW to trigger reconfig loop back to step 0 from sys_proc_fab_iovalid if: 1) sys_proc_fab_iovalid rc = FAPI2_RC_SUCCESS -- AND -- 2) new output o_obus_dl_rcs (vector of P9_FAB_IOVALID_DL_NOT_TRAINED_ERR rc objects identifying links which failed on this chip) has entries - attribute changes: ATTR_LINK_TRAIN -- remove platinit tag, attr should init to zero (both even and odd), and reconfig loop will adjust value as we go Change-Id: I95eebd2b893db6d2511aae40798c0a4e049835d6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59022 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59037
* p9_setup_clock_term: Apply tweak bits, put oscswitches into resetJoachim Fenkes2018-06-011-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | Put the oscswitches into reset by deasserting PGOOD before we turn on clocks, to make sure they fall into a reliable defined state when we assert PGOOD during p9_clock_test. Update the set values of root controls with preliminary sys oscswitch tweak bits; to be refined after full redundant oscillator bringup. Refactor some code to make procedure more readable. Change-Id: Ib634d135b1932c2b7d5d88ba1689c5e3a20a9c7e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58826 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59053 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_common -- mark TP LFIR bits 18:20 recoverableJoe McGill2018-06-011-2/+2
| | | | | | | | | | | | | | | Change-Id: I641636e54dcc615cdf8f2de6f43d6878275113bf CQ: SW427932 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59591 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59606 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding p9c 1.3 support.Soma BhanuTej2018-05-255-34/+56
| | | | | | | | | | | | | | | Change-Id: I6ec5550871bcdbab64749bd90f2f8bf4354fd2b8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58400 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58568 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable 2-for-1 on NDD2.2- and CDD1.2-Nick Klazynski2018-05-181-4/+5
| | | | | | | | | | | | | | Change-Id: I3f0069525af2c76a07b6a28bfeb6ef6a0b3c3cf9 CQ: HW447773 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58973 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58984 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* enable spreading via SS PLL for Fleetwood platformJoe McGill2018-05-173-4/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pervasive_attribues.xml: Create new platinit attribute -- ATTR_MRW_FILTER_PLL_BUCKET System specific value for Filter PLL bucket selector (init=0), set by MRW - if non-zero, this value will directly set ATTR_FILTER_PLL_BUCKET, which is used by SBE to select the override to apply - if zero, MVPD MK keyword will set ATTR_FILTER_PLL_BUCKET p9.filter.pll.override.scan.initfile: Repurpose overrides built for Cumulus, to produce 0.2% down spread Nimbus overrides still enable control of BGoffset p9_xip_customize.C: Consume ATTR_MRW_FILTER_PLL_BUCKET and use logic above to set ATTR_FILTER_PLL_BUCKET Change-Id: I2ea799179632d36251027a1d4468c6c89bfa6e00 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57988 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58003 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable full ERAT for NDD2.2+ and CDD1.1+Nick Klazynski2018-05-171-0/+24
| | | | | | | | | | | | | | | | Change-Id: I1f7d43402b5e99936941ab3345bc8c69e33d2213 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58789 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58796 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SBE:PUTRING: Add callout support for checkword mismatch failurePrasad Bg Ranganath2018-05-171-1/+21
| | | | | | | | | | | | | | | Change-Id: Ie8fab7647498e7dc753991fc3a94bbfed44506a6 CQ:SW429285 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58884 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58887
* Update to p9_xip_tool to handle stand-alone DDCO ring files.Claus Michael Olsen2018-05-173-186/+302
| | | | | | | | | | | | | | | | | | | | | | | | | | | In this update, we're adding support to p9_xip_tool to be able to dissect and extract stand-alone DDCO ring files, i.e. files that are DD packaged through using the dd_container API and which is the DD packaging that XIP "understands". Right now, dissect and extract (of a specific DD level) can only be achieved if the DDCO binary is attached to the XIP image as one of the rings sections, .rings, .overlays or .overrides. Key_Cronus_Test=XIP_REGRESS Change-Id: I8be00742f05b4df61652a1de6d0230bb5d203f97 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54704 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54713 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HW447585, HW447589, HW439303, Fix CDD1.2 security settingNick Klazynski2018-05-171-1/+84
| | | | | | | | | | | | | | | | | | | Change-Id: I5dc3d85b0e77109c5d05fe49796936dceb1313ee CQ: HW447585 CQ: HW447589 CQ: HW439303 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58528 Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58539 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Fix FFDC collection for HWP p9_collect_suspend_ffdc.Prem Shanker Jha2018-05-172-179/+199
| | | | | | | | | | | | | | | | | | | | | Commit addresses some coding errors in HWP. As a result of these FFDC variables were getting populated with register data. Commit also adds HWP wrapper for assisting debug in cronus environment. Key_Cronus_Test=PM_REGRESS CQ: SW427994 Change-Id: I5acff6bf85b5cfb9b1a582cb879dcb282e9d6809 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58417 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58430 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding p9c DD13 supportSoma BhanuTej2018-05-111-0/+7
| | | | | | | | | | | | | | | | | | | | -> p9_sim_model_boot.C -> p9_frequency_bucket.H -> cronus_auto_settings.H Change-Id: Ic3b099c7e43d673d861c83f33caede27f9b5d10e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58402 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58455 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Nest perf counter cfg registersSantosh Balasubramanian2018-05-101-0/+65
| | | | | | | | | | | | Change-Id: I3da29182a99e6f1bcdeaa8e1312728098e727735 CQ: SW428146 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57876 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57896 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* jgr18042600 Changed rx_recal_abort_dl_mask=0 for cumulus HW446964John Rell2018-05-041-0/+24
| | | | | | | | | | | | | | | | | Change-Id: Id3f996b089f2c11581b6f6906a24033cebca9ad3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57920 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Christopher W. Steffen <cwsteffen@us.ibm.com> Dev-Ready: John G. Rell III <jgrell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57922 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Risk level 3/4/5 support: Step 2 - image update to TOR v7Claus Michael Olsen2018-05-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | - This commit updates the image ring sections to TOR v7. - It will fail with EKB FSP CI until we include the prereq to the merged step 1 commit in PPE and HB. Key_Cronus_Test=XIP_REGRESS cmvc-prereq: 1053262 cmvc-prereq: 1053182 Change-Id: Ie7452fe42877297da4f0da5cd4e51c989b6ac28d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57421 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57432 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Savory Insomnia -- revert to ordered tlbie mode for CumulusJoe McGill2018-05-033-3/+62
| | | | | | | | | | | | | | | | | | | | | | - configure the fabric & unit snooper logic to operate in ordered/p8 tlbie mode - prohibit the nest mmu from snooping tlbie - adjust NCU tlbie stall settings - revert HW419330 fix on Cumulus only Change-Id: Idf18f81b08c4fb6e372fa4c544c023a8820bb37b CQ: HW440920 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56406 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56415 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* TM workaround for HW443982Nick Klazynski2018-05-031-4/+11
| | | | | | | | | | | | | | | | Change-Id: Ic688e695c6eb6589b88b76b4ecefa252b045bdf9 CQ: HW443982 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57189 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57197 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Fixes for Livelock ScenariosRahul Batra2018-04-261-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | -Fixes DPLL Ownership issues during Pstate Start -Fixes WOF Enablement and Quad/Core Active Update(STOP11/5) livelock scenario -Fixes PM Complex Suspend and Quad/Core Active Update(STOP11/5) livelock scenario -Fixes VDM Droop Suspend STOP entries livelock scenario Key_Cronus_Test=PM_REGRESS Change-Id: I14a0dece4c74bc04618f7d1f3838dbe273bace94 CQ: SW425778 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57191 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: YUE DU <daviddu@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57255 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Risk level 3/4/5 support: Step 1 - backward compatibility and v6 imageClaus Michael Olsen2018-04-244-56/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Introducing RV_RL3/4/5 ring variant (RV) support for EC/EQ chiplets. - Dropping RV support for all chiplet's instance rings which saves 456 Quad bytes and 58 Nest bytes in Seeprom's TOR slots (compared to master). - Each additional risk level adds 144 bytes in Seeprom TOR slots. - Various changes to data names associated with ring variants to clarify that the notion of ring variants is now specific only to Common rings while Instance rings only have the BASE variant. - Also, removed backwards compatibility to TOR v5, i.e. from before we introduced RL2 in february. Assumption is that all images/drivers used in fips910/920 and OP920 are TOR v6. - This commit produces a TOR v6 image to ensure EKB FSP CI success. Key_Cronus_Test=XIP_REGRESS Change-Id: Icfcb1e68fd74a10ffc48ee7a5da528a8042ef3b1 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56973 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Kahn C. Evans <kahnevan@us.ibm.com> Reviewed-by: James N. Klazynski <jklazyns@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56982 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding p9n 2.3 support and p9n 2.3/p9c 1.2 security updateBen Gass2018-04-205-44/+103
| | | | | | | | | | | | | | | | CMVC-Prereq: 1051830 Change-Id: I21b0d9187443f2727f83df310bca2fb3ae0fd80c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55376 Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56834 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Revert changes to EFF_FBC_GRP_CHIP_IDS modespashabk-in2018-04-202-7/+5
| | | | | | | | | | | | | | | | Change-Id: I4907eea62c2fa85bdf9ed193d1820fba84afc82f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57530 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57534 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Clean up PM Reset and PM Complex SuspendChristian Geddes2018-04-201-2/+2
| | | | | | | | | | | | | | | | | | | | - Increase timeout in PM Complex Suspend from 10ms -> 500ms - Disable CME monitoring of PGPE heart beat loss before halting PGPE Key_Cronus_Test=PM_REGRESS Change-Id: I3fbb435ce694e7590e9e9570107347a621828402 CQ: SW424102 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56884 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56903
* make ATTR_START_CBS_FIFO_RESET_SKIP platInitMatt K. Light2018-04-181-0/+1
| | | | | | | | | | | | | | | Change-Id: Ia995817f30cca235b8c725feec27f7a14f26f924 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43311 Dev-Ready: Matt K. Light <mklight@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43317
* Adding changes to handle core checkstopsElizabeth Liner2018-04-182-2/+23
| | | | | | | | | | | | | | | | | | | | | At certain points during the IPL, we need to turn off unit checkstops and switch them to system checkstops. This HWP saves off the original value, turns unit to system checkstops, and then later restores them. Change-Id: Iebd1d4c5b69eae04f05b890c879d8dd88f0655d3 RTC:147565 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56331 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_hcd_cache_scominit -- disable LCO unless using force_all_coresJoe McGill2018-04-181-2/+2
| | | | | | | | | | | | | | Change-Id: I938d01f60907444b65b2f3b08d0fdfc59433dc79 CQ: SW424941 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57399 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57404 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fenced Enabled check along with vdd_pfet_disable_core for scomsRaja Das2018-04-171-6/+16
| | | | | | | | | | | | | | | | | In core stopstate2, only checking the vdd_pfet_disable_core is not enough before scoming for C_CLOCK_STAT_SL, since in stopstate2 fences are up, so need to check for fenced bit as well in C_NET_CTRL0 reg. Change-Id: If99dd3d357b6e07c56417edae0868c03f2f0b720 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52993 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53809
* Consume PROC_MEM_TO_USE for alt memory configspashabk-in2018-04-164-26/+25
| | | | | | | | | | | | | | | Change-Id: Ideb3c3d2bbdbce8b773d51b86d9f97f2e654ca56 RTC:189091 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56197 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56203
* Add PROC_MEM_TO_USE to SBEspashabk-in2018-04-131-1/+1
| | | | | | | | | | | | | Change-Id: I614bf9b59166dadd84ea5276845f2cd7d897c2cb Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57053 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Elizabeth K. Liner <eliner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57056
* Temporarily moving attribute to the system targetElizabeth Liner2018-04-101-0/+12
| | | | | | | | | | | | | | | | | | | | There were dependency issues between the FSP and hostboot changes. This commit is temporarily moving everything to the system target, so that we can get our changes through CI. We'll go back later and fix the target to the proc Change-Id: Ic2d63d10afe50342290a814a94fd2d07d7102fdf RTC:176434 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56814 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56825
* Abist proc update for SBE changesAbhishek Agarwal2018-04-092-0/+21
| | | | | | | | | | | | | | | Change-Id: I28a11ecc5f64498f495f1575c914c5d3120c6f23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54243 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56789 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* security whitelist -- add X0 instance of DL IOE control registerJoe McGill2018-04-051-0/+1
| | | | | | | | | | | | | | | | | X1, X2 instances were added previously for Nimbus, but missed X0 instance physical address needed in Cumulus Change-Id: Iece6927e63eb0c7d432d078ef22f29b245a233b0 CQ: SW423484 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56774 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56775
* p9_sbe_lpc_init: Fix cycle sim delay loopSoma BhanuTej2018-04-051-2/+3
| | | | | | | | | | | | | | | | | | Adding additional delay during polling for LPC status Issue encountered in GSD2PIB mode Awan simulations only Change-Id: I220843de8c37fa578ea26ea253345a380666a1d7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56724 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56779 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* move xlink psave configuration to SBEJoe McGill2018-04-031-1/+29
| | | | | | | | | | | | | | | | | | | | | | | 55058 added inits to prime the PPE for xlink psave the register touched is in the blacklist, so it can't be touched on slave chips via FSI in the ioe tl SCOM initifle -- this was triggering HW CI failures this commit simply shifts the register setup into the SBE, where it can be performed securely Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059 CQ: SW421691 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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