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path: root/src/import/chips/p9/procedures
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* p9_setup_clock_term updatesAnusha Reddy Rangareddygari2017-10-241-3/+5
* Cumulus proc updatesAnusha Reddy Rangareddygari2017-10-231-1/+4
* Level 2 HWP for p9_setup_clock_termAnusha Reddy Rangareddygari2017-10-231-13/+36
* L1 Rev istep 0.(6-8,11,13,14),1.1,2.(1-13,15,18-20,22,26,27,30,32,34) V2Abhishek Agarwal2017-10-231-0/+62
* Additional checks to p9_extract_sbe_rcSoma BhanuTej2017-10-231-0/+17
* VDM: p9_pstate_parameter_block check for VDM Large threshold < -32mVGreg Still2017-10-151-1/+19
* PLL updates for filter BG, BW including OBUS tank coreqsJoe McGill2017-10-141-2/+49
* Use compiler definition for size_tSachin Gupta2017-10-131-2/+2
* Updating L2 re-request jitter settings for CumulusLuke C. Murray2017-10-121-0/+17
* Workaround for HW421347 Scandalous PieLuke C. Murray2017-10-121-0/+25
* HW415883 applies to NDD2.1, Add JellyVector WAT, add HW422495, add HW421831Nick Klazynski2017-10-122-15/+16
* Share common code between p9_l2_flush and p9_l2err_linedeleteThi Tran2017-10-113-131/+161
* p9_sbe_chiplet_reset: Set VITL_AL flag for MC chipletsJoachim Fenkes2017-10-092-0/+6
* p9_sbe_tp_enable_ridi -- restore old behavior for cache contained mode supportJoe McGill2017-10-061-1/+24
* New PPE state dump utilityAmit Kumar2017-10-051-0/+37
* PM (Cronus): Add processor id for errors from p9_activate_stop15_coresGreg Still2017-10-051-0/+20
* PM: PPE State tool fixes.Prem Shanker Jha2017-10-051-131/+41
* Revert PLL unlock commits of 45102 and 46563Yue Du2017-10-053-21/+3
* SIBRC detailsAshish2017-10-051-142/+65
* code bug: single step was not restoring dbcrAshish2017-10-051-1/+2
* p9_ppe_commands: add -step_trap supportGreg Still2017-10-051-1/+210
* p9_ppe_commands : Enhanced single stepAshish2017-10-051-35/+178
* PPE command line controlAshish2017-10-051-0/+485
* p9_thread_control -- remove threads_running check from sreset, start code pathsJoe McGill2017-10-042-113/+0
* Update default case in set_sbe_errorRichard J. Knight2017-10-041-0/+1
* {nest,cache}_pll_setup: Properly clear PLL unlock indicationJoachim Fenkes2017-10-042-3/+9
* PM (Cronus): Add processor id for errors from p9_activate_stop15_coresGreg Still2017-10-041-0/+13
* PM: PPE State tool fixes.Prem Shanker Jha2017-10-041-15/+304
* SIBRC detailsAshish2017-10-041-8/+77
* p9_ppe_commands: add -step_trap supportGreg Still2017-10-041-6/+6
* p9_ppe_commands : Enhanced single stepAshish2017-10-041-10/+25
* PPE command line controlAshish2017-10-041-0/+150
* Remove HB incorrect setting of ATTR_DD1_SLOW_PCI_REF_CLOCKThi Tran2017-10-041-1/+1
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-0470-103/+103
* Add workarounds for HW421426 and HW422629, Swap IMCs aroundNick Klazynski2017-10-041-0/+41
* Remove functionality from tp enable ridi and move it to nest enabled ridiChristian Geddes2017-10-023-26/+47
* PM: p9_pm_init, p9_pm_utils clean-upGreg Still2017-10-022-33/+35
* update HWP level metadata for nest, common filesJoe McGill2017-10-022-59/+64
* Expanding MCU tag fifo settings to be freq dependent.Lennard Streat2017-10-021-0/+21
* STOP: Properly clear DPLL unlock indication in dpll_setupYue Du2017-09-291-0/+11
* STOP: attribute to halt upon phantom interruptsYue Du2017-09-292-1/+56
* STOP: Fix MPIPL Dpll Lock via ensuring mode 1Yue Du2017-09-271-1/+9
* updates for NPU errataJoe McGill2017-09-271-2/+69
* Added Nimbus & Cumulus attributes for INT initfilesDavid Kauer2017-09-271-6/+38
* Increment red_waterfall for low vdn fixJacob Harvey2017-09-271-1/+19
* Set override flag for lots of PM attributesDan Crowell2017-09-271-1/+41
* SAFE mode:moved writing safe mode value from istep 6 to istep 10Prasad Bg Ranganath2017-09-241-13/+10
* PM: Move to chip EC based #V validity checking in p9_pstate_parameter_blockGreg Still2017-09-222-1/+52
* Allow request fused mode bit when in HW fused modeDean Sanner2017-09-221-2/+4
* PM/MPIPL: p9_quad_power_off Level 3Greg Still2017-09-213-34/+65
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