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path: root/src/import/chips/p9/procedures/xml
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* L3 updates -- p9_build_smp, p9_fbc_utilsJoe McGill2017-05-282-316/+30
* p9_perv_sbe_cmn: Level 3Joachim Fenkes2017-05-271-1/+57
* p9_pstate_parameter_block: Pound W enhancement for VID ComparePrasad Bg Ranganath2017-05-271-0/+22
* Updated memory DD1 vs DD2 attributeStephen Glancy2017-05-251-2/+2
* L3 update -- p9_sbe_scominitJoe McGill2017-05-251-7/+21
* PM: Remove Queued Scan attribute and image buildMichael Floyd2017-05-251-15/+0
* Update core inits for DD2Nick Klazynski2017-05-241-5/+314
* PM: add defaults for AVSBus attributesGreg Still2017-05-241-2/+24
* L3 update -- p9_fbc_eff_configJoe McGill2017-05-241-1/+2
* p9_cen_ref_clk_enable -- p9 initial versionPeng Fei GOU2017-05-241-3/+6
* Level 3 : OCB & OCC proceduresSangeetha T S2017-05-192-5/+54
* p9_sbe_nest_initf -- add HWP support to scan n3_br_fureJoe McGill2017-05-191-0/+5
* Adds DCD calibration control attributesStephen Glancy2017-05-191-0/+17
* Initfile updates for FBC DD2dchowe2017-05-161-0/+18
* p9.int.scan.initfile -- init PSIHB to LSI modeJoe McGill2017-05-141-0/+17
* Add DLL workaround and unit testsAndre Marin2017-05-121-54/+73
* p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2017-05-111-0/+9
* NMMU Nimbus dd2 scom/scan updates, updated commentsEmmanuel Sacristan2017-05-112-0/+86
* Implementing Michael Floyds improvements.Michael Koch2017-05-111-5/+37
* Added DQS alignment workaroundStephen Glancy2017-05-111-0/+19
* dd2 initsShelton Leung2017-05-111-34/+103
* p9.xbus.pll.scan.initfile -- restore full frequency settings for Nimbus DD2+Joe McGill2017-05-111-0/+18
* Update INT DD2 initfilesDavid Kauer2017-05-111-0/+17
* Updates for P9 NX DD2 initfilesChris Hanudel2017-05-111-54/+72
* ADU Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-111-11/+96
* PBA Level 3 code, changed owner to Josh, and added commentsCHRISTINA L. GRAVES2017-05-111-10/+157
* derate NVLINK frequency for Nimbus DD1Joe McGill2017-05-051-0/+17
* Performance updates for HW409069Luke Murray2017-05-051-0/+25
* Reserving HTM QueuesThi Tran2017-05-051-0/+17
* WOF: Additional fields needed in OCC Pstate Parameter block for WOFPrasad Bg Ranganath2017-05-051-0/+18
* p9_mss_setup_bars -- customize interleave granularityJoe McGill2017-05-041-0/+30
* p9_sbe_attributes.xml -- add entries for effective FBC IDsJoe McGill2017-05-041-0/+8
* Change RD_CTR workaround val and update attr nameJacob Harvey2017-04-281-8/+8
* L3 initfile updatesAlex Taft2017-04-281-17/+18
* Adding HW401552 to cxa initfile to workaround clockgating bugJenny Huynh2017-04-281-0/+17
* WOF: VRM timing, WOF and VDM enblement attributes additionsPrasad Bg Ranganath2017-04-281-1/+130
* Disable cp_me from the L3 for Nimbus DD1 and DD2.0.Luke Murray2017-04-281-0/+17
* INT scan initfile change to add workaround for HW408972Jenny Huynh2017-04-281-0/+18
* Updating HW363605 workaround to be applied to all chipsLuke Murray2017-04-281-17/+0
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2017-04-201-0/+18
* p9_pstate_param_blk: Define VFRT table and initialize the dataPrasad Bg Ranganath2017-04-191-0/+37
* PM: Resonant Clocking Enablement - InfrastructureChristopher M. Riedl2017-04-191-6/+6
* Add unique FAPI RC per PIB RCSantosh Puranik2017-04-181-1/+43
* STOP: Enable CHTMYue Du2017-04-181-0/+38
* Added read ctr bad delay workaroundStephen Glancy2017-04-181-0/+17
* Updating optimal larx/stcx dials for performanceLuke Murray2017-04-181-0/+24
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2017-04-181-0/+19
* FFDC updates - p9_start_cbsAnusha Reddy Rangareddygari2017-04-061-1/+13
* Update filter pll settings as per HW407180Ben Gass2017-04-061-0/+18
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-04-062-0/+24
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