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path: root/src/import/chips/p9/procedures/xml/attribute_info
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* Updates to run HW VREF cal by defaultStephen Glancy2017-02-251-0/+34
* HW399609: DD1 changing core/nest hang limit or hang pulse dividerYue Du2017-02-241-0/+4
* adjust SRAM timingsJoe McGill2017-02-241-19/+2
* PM: add ATTR_PGPE_HCODE_FUNCTION_ENABLE attribute to control PGPE opsGreg Still2017-02-241-0/+27
* New dummy pulse pok bits (for L2/L3)Alex Taft2017-02-241-0/+34
* NPU scan/scom init updatesRyan Black2017-02-211-0/+17
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2017-02-211-1/+52
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-02-211-0/+20
* Removing ATTR_PROC_FABRIC_ADDR_BAR_MODEThi Tran2017-02-212-19/+0
* Make ATTR_CHIP_UNIT_POS virtualSantosh Puranik2017-02-191-65/+2
* reverting FIRs to master values, setting only bit 8Juan Medina2017-02-161-0/+19
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-02-162-0/+20
* adding insert for soft fail threshold for dd1 and dd2Joshua Hannan2017-02-151-0/+17
* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2017-02-151-2/+53
* p9_pfet_init: remove PFET attributes as they have no real valueGreg Still2017-02-101-89/+0
* Update pm_plat_attributes with defaults and better descriptionsGreg Still2017-02-081-41/+141
* amo cache disabled for dd1 for HW401780Shelton Leung2017-02-061-0/+17
* ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE attribute in SBEspashabk-in2017-02-031-0/+4
* Adding HW363780 to NPU scom initfilesJenny Huynh2017-02-021-0/+18
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2017-01-311-0/+137
* Control NDL training updateAnusha Reddy Rangareddygari2017-01-312-1/+14
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-01-311-0/+18
* workaround for hw400932 atag corruptin in prespShelton Leung2017-01-311-0/+17
* dd1 workaround for hw400075 coherency errorShelton Leung2017-01-251-0/+17
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-01-241-0/+17
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-01-242-24/+2
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-01-242-0/+21
* FBC updates for HW383616, HW384245Joe McGill2017-01-242-2/+36
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-01-241-0/+34
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-01-221-0/+1312
* Adding skip group dials for cache when chip=groupLuke Murray2017-01-221-0/+41
* Set plck as default mode in ATTR_BOOT_FLAGSSantosh Puranik2017-01-221-1/+1
* p9_sbe_chiplet_reset -- drive PCIE PLL from SS filter PLL for DD1.xJoe McGill2017-01-171-1/+5
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-01-161-0/+18
* configure FBC pump mode in SBEJoe McGill2017-01-151-5/+4
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-01-151-0/+34
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-01-041-35/+1
* Security control override disable support - p9_setup_sbe_configSoma BhanuTej2017-01-041-19/+1
* p9.fbc.scan.initfile -- clock off MCSYNC staging latchesJoe McGill2017-01-011-0/+18
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-202-0/+21
* PM: Added support for CME/SGPE flags in respective image header.Prem Shanker Jha2016-12-201-0/+18
* Add Memory Subsystem FIR supportBrian Silver2016-12-201-0/+17
* Adding in defect HW395947,HW930007 to INT initfilesJenny Huynh2016-12-201-1/+72
* Add EC workaround for PHY training bad bit processingBrian Silver2016-12-201-1/+20
* scan inits for lab workaround for DI bug HW392781Shelton Leung2016-11-301-0/+17
* Remove unused SBE attributesSantosh Puranik2016-11-281-126/+1
* Adding workaround for HW930007 and HW386013Jenny Huynh2016-11-211-0/+18
* p9_sbe_lpc_init fix with GPIO resetCHRISTINA L. GRAVES2016-11-212-0/+20
* p9_sbe_attr_setup updatesAnusha Reddy Rangareddygari2016-11-212-0/+5
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-212-1/+22
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