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path: root/src/import/chips/p9/procedures/ppe/pk/ppe42
Commit message (Expand)AuthorAgeFilesLines
* HCODE Make divide using DERP/DORP atomicDouglas Gilbert2018-08-231-1/+7
* CME Code Size Reduction ATTEMPT#3Michael Floyd2018-02-072-2/+26
* Register FFDC call is handled within machine_check_handlerRaja Das2018-01-191-4/+5
* PPE: Adjust the maximum decrementer countDoug Gilbert2017-12-151-2/+5
* PPE empty PK FFDC handler to save-off required registersRaja Das2017-11-202-2/+20
* Use compiler definition for size_tSachin Gupta2017-10-131-2/+2
* PK,IOTA: Enter idle state at a known locationDoug Gilbert2017-09-142-1/+22
* Halt on zero instruction/load/store addressAdam Hale2017-08-112-2/+9
* STOP: Restore MSR in UIH hookYue Du2017-06-301-0/+5
* Fix DD LEVEL to support minor ECsMichael Floyd2017-06-292-2/+2
* DERP/DORP Implementation for pgpe dd2Doug Gilbert2017-06-222-4/+76
* PK trace fixes and ppe42 optimizationsDoug Gilbert2017-06-222-7/+7
* Remove context switch in ppe program exception handlerspashabk-in2017-05-241-8/+1
* PK move global data to .sdata/.sbss sections to reduce code sizeDoug Gilbert2017-04-191-3/+3
* PK DEC timer interrupts too close togetherDoug Gilbert2017-04-181-9/+11
* STOP: optimize size of stop imagesYue Du2017-02-251-1/+6
* putring/CME error code supportGreg Still2017-02-241-0/+4
* PK: make GPE using 8B in64/out64 opYue Du2017-01-181-31/+0
* PK stack checkingDoug Gilbert2017-01-172-7/+19
* HW398189: mask SIBRC = 6 in CME MSR under NDD1Yue Du2017-01-082-2/+28
* Remove PPE_LIBPATH.Doug Gilbert2016-10-311-4/+4
* ppe42 Icache aligned divideDoug Gilbert2016-10-313-45/+60
* PPE Fixed Interval Timer handler bug fixesRahul Batra2016-10-183-7/+3
* Add comments for MSR bit descriptionsDoug Gilbert2016-10-141-3/+8
* SGPE and CME scanning integrationGreg Still2016-10-101-1/+1
* Create new PK div32.S file to prime repository mirroringDoug Gilbert2016-09-301-0/+25
* Update file headersSachin Gupta2016-09-168-8/+8
* GPE PK PBA setup APIDoug Gilbert2016-09-133-3/+46
* PK remove IBM confidential and redundant copyright sectionsDoug Gilbert2016-09-1321-176/+75
* Set default MSR for performanceDoug Gilbert2016-09-092-6/+22
* MSR read gets re-ordered in codeDoug Gilbert2016-09-072-5/+5
* SBE move import`Shakeeb2016-09-0129-0/+6019
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