| Commit message (Collapse) | Author | Age | Files | Lines |
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62028 added a workaround for SW 430383, using a manual re-scan of the ring
hardcoded to flip the desired bits because engineering data was not yet
available for the necessary spies
This commit removes the SBE manual scan sequence and sets the necessary
chicken switches by the newly added spy entries
Change-Id: I912f190ab44c320f9bd142ce626570d34ec0b00f
CQ: SW438480
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62675
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62710
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_mss_eff_grouping.C:
- determines whether secure mem is requested, reserves smf space
- always reserve smf at end of range because of end-of-range bit
- set addr15 when reporting smf base address
- mask off group_id(0) via chip address extension if smf is enabled
- updated to set value of attr_smf_enabled
- enhanced error reporting with smf config/supported values
- made values reported to attr_mss_mcs_group_32 more clear
p9_mss_setup_bars.C:
- set MCFGPA/MCFGPMA registers with SMF data
- fixed scom registers for MCFGPA/MCFGPMA hole setup
- added note to leave MCFIR_invalid_smf masked for HW451708/HW451711
- added assert to check for HOLE1 and SMF enable overlaps
p9_query_mssinfo.C:
- updated to print out SMF reservations
- print out HTM/OCC/SMF reservations regardless of mirroring enable
p9_fbc_utils.C:
- prevent group_id(0)=1 from affecting mappable memory ranges
p9_sbe_fabricinit.C:
- mask off group_id(0) via chip address extension if smf is enabled
p9_setup_sbe_config.C, p9_sbe_attr_setup.C:
- use scratch_reg6 bit(16) to pass smf_config value
initfiles:
- removed setup to use other addr bits as secure bit; core only uses addr15
- added setup for ncu addr15 value in hcode
- always set addr15 config bit in bridge unit if smf is supported
- set addr15 bit across all mcs if smf is enabled
- added in settings to enable smf in nmmu unit
- hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported
attributes:
- ATTR_SMF_ENABLE is a system level attribute
- changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported)
CQ:HW451708
CQ:HW451711
Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I2d9aed7833a1bf43c797689d50ff32794ef54cff
CQ: SW430383
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62028
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62042
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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On Cumulus, set up the oscerr mask (0102001A) such that errors on
unused MF/PCI oscillators are masked (based on the setup in RC3),
making sure the corresponding FIR bit (TP LFIR bit 37) will not
report false positives.
Keep the mask constant for Nimbus as only MF oscillator 0 is in use
there.
This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5
because a correct mask setting here obviates the need for selective
FIR masking.
Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Add an external FFDC collection procedure that will dump the LPC
register spaces, make sure it is called if after LPC setup an OPB
error is registered.
Change-Id: I91046a6a3814ba94abd878f860e08f1b1338390b
CQ: SW435433
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57803
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60994
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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During the clock_test2 substep, the procedure would unconditionally
clear use_osc_1_0 from ROOT_CTRL3, which turns the use_osc field (that
has been set up in istep 0) into an invalid value and breaks redundant
PCI clock failover.
Not removing that piece of code altogether because it does not appear
to hurt anything on Nimbus and it was explicitly requested by Uli back
in the Nimbus days, even though we don't remember his rationale.
Change-Id: Ieffe1946980a65c302f60d80f83b527e24d74b3b
CQ: SW434930
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61188
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61230
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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1. On PENDING/INVALID_STATE RCs, need some FFDC and service actions on FSP
using regular FAPI mechanisms like FAPI_ASSERT and register ffdc colletion
2. SBE still uses existing mechanism and restrictions - optimized for space
a. no fapi error xml based callbacks
b. no fapi error xml based register ffdc collection
c. max local ffdc members < 20
d. depends on p9_collect_deadman_ffdc for FFDC with RC TIMEOUT
3. Compile out extra code on SBE builds
Change-Id: Id35f9a7dbfc7e423bd7cf0846f493a8270a48cd6
CQ: SW430391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60320
Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60391
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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TP LFIR 37 is meant to be marked recoverable for Cumulus
60118 unmasked the bit, but the default action register settings
are programmed to trigger a checkstop. This adjust the action1 register
default to recoverable.
Change-Id: I8d07fdac8eb060ba10929133fdbe93621b8b53e7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60244
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60261
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Put the oscswitches into reset by deasserting PGOOD before we turn on
clocks, to make sure they fall into a reliable defined state when we
assert PGOOD during p9_clock_test.
Update the set values of root controls with preliminary sys oscswitch
tweak bits; to be refined after full redundant oscillator bringup.
Refactor some code to make procedure more readable.
Change-Id: Ib634d135b1932c2b7d5d88ba1689c5e3a20a9c7e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58826
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59053
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I641636e54dcc615cdf8f2de6f43d6878275113bf
CQ: SW427932
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59591
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59606
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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pervasive_attribues.xml:
Create new platinit attribute -- ATTR_MRW_FILTER_PLL_BUCKET
System specific value for Filter PLL bucket selector (init=0), set by MRW
- if non-zero, this value will directly set ATTR_FILTER_PLL_BUCKET,
which is used by SBE to select the override to apply
- if zero, MVPD MK keyword will set ATTR_FILTER_PLL_BUCKET
p9.filter.pll.override.scan.initfile:
Repurpose overrides built for Cumulus, to produce 0.2% down spread
Nimbus overrides still enable control of BGoffset
p9_xip_customize.C:
Consume ATTR_MRW_FILTER_PLL_BUCKET and use logic above to
set ATTR_FILTER_PLL_BUCKET
Change-Id: I2ea799179632d36251027a1d4468c6c89bfa6e00
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57988
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/58003
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Adding additional delay during polling for LPC status
Issue encountered in GSD2PIB mode Awan simulations only
Change-Id: I220843de8c37fa578ea26ea253345a380666a1d7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56724
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56779
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Add a "SBE security backdoor" bit to reflect the state of the SBE
security backdoor; the bit is passed to the hostboot bootloader from SBE.
The new bit is the inverse of the ATTR_SECURITY_MODE attribute.
Also bump the version of SBE/bootloader to reflect the change.
Change-Id: Idf3009447c51c66306c043daf7f8189b8cbf2f36
RTC:188961
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56309
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Michael Baiocchi <mbaiocch@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56318
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Change-Id: Ided77a0645e4f657b326ba5ec63f7c35ab6b2029
CQ: SW421112
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55906
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/55907
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Factor LPC register access out into its own utility function, with
added timeout for the ADU access and proper FFDC if the ADU times out.
CQ: SW418354
cmvc-prereq: 1048349
Change-Id: Ief05ccb022eeb1ec45d2f49f386fb58231966058
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54637
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54641
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ib21a9940b9b458a74d24a4a6bf1ad734ec4896c3
CQ: SW419535
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54951
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Daniel J. Henderson <hende@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54955
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As a carryover from prior projects, PRD code currently contains logic which
attempts to restart the core trace arrays (via the SBE HWP) after processing
a recoverable error emitted from the core.
The current HWP flags an error in this case (indicating that the core
trace arrays are not SCOM retrievable, which is true for all levels of p9).
This generates a customer visible error log with a FW type callout, which
is undesirable.
This patch is intended to satisfy the current PRD call which intends to reset
and start the core traces, without triggering the check mentioned above or
attempting to access non-implemented SCOM registers.
Ultimately it should have no effect on the actual core tracing, which is
managed on p9 by non-SCOM accessible logic in PC. I confirmed with Jim Bishop
that the PC logic will not stop tracing on recoverable errors, so there should
be no exposure.
Change-Id: I77e47f71d18b6a3a762ab52b0f6b42d022153f3b
CQ: SW418341
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54857
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Kevin F. Reick <reick@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54861
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I0960ec588156f3df3f863b6c5fa41bbed95e089e
RTC: 183048
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53139
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Dev-Ready: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: NAGENDRA K. GURRAM <nagendra.g@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53152
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: If904019d1a847136be3e553302ab5e29ae0a8f23
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54482
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54508
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This commit changes the images' .rings section by adding the TOR
RL2 variant slot to the runtime Quad chiplets, EQ and EC.
Specifically, we have changed the definition of the ATTR_RISK_LEVEL
attribute to now have three risk levels, RL0 (prev FALSE), RL1
(prev TRUE) and RL2 (new). To accomodate RL2, a new "override"
txt file has been created, ./attribute_ovd/runtime_risk2.txt and
changes to many other files using the ATTR_RISK_LEVEL attrib have
been updated as well.
Lastly, and to allow for the inclusion of RL2 rings in the HW
image, the TOR_VERSION has been updated to version 6 which will
allow for RL2 support in the ring ID metadata files.
p9_setup_sbe_config is updated to write the RISK_LEVEL value into
scratch 3 bits 28:31, and deprecate the existing mailbox.
RISK_LEVEL processing has been removed from p9_sbe_attr_setup. It's
only function is to seed mailboxes which are empty via the
attribute state present in the SEEPROM. Since RISK_LEVEL is zero
at image build time, and explicitly cleared as a result of every
customization, there's logically no need to process the RISK_LEVEL
here.
PPE changes to accomodate the new RISK_LEVEL mailbox
location need to be implemented in the PLAT code: src/hwpf/target.C
Key_Cronus_Test=XIP_REGRESS
HW-ImageBuild-Preqeq=52659
- 52659 must be fully merged in Cronus and HB before this commit
(53292) can be merged. This is to avoid a Coreq situation.
CQ: SW416424
cmvc-prereq: 1046058
cmvc-prereq: 1043606
cmvc-prereq: 1045920
Change-Id: Ia0471219916602cc0041a2c55a1070013f66a7d9
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53292
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53322
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Change-Id: Ib8940710cadc62228be70bf60e98673ece171e10
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54024
Reviewed-by: PRADEEP N. CHATNAHALLI <pradeepcn@in.ibm.com>
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54025
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This reverts commit 59635779caa45afd1be7e483d232bb317b6c0989.
Change-Id: I93708f97e5a5c44e9af1957230bb68a754e98ebb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52838
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Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/53499
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I145734f290153eb6f7bc9810917026260d490260
CQ: SW413535
Backport: release-fips910
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52513
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Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com>
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52521
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That delay was always compiled into the procedure and we tested with
it, so let's make it permanent.
Change-Id: If8a5c6fbf4bd8b42e37656f66ced96604813485b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48748
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Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48754
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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The PCI oscillator checking code in proc_clock_test2 always checked both
osc error bits, which fails on a Cumulus system with only a single PCI
refclock active. Modify it to check osc error bits depending on which
oscillators have been configured in the osclite config.
Change-Id: I8c5ee38f8bc718dbb8eab59139a19800bb3a9f6f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51723
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Reviewed-by: Martin Padeffke <padeffke@de.ibm.com>
Dev-Ready: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51796
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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pervasive_attributes.xml
sbe_attributes.xml
create ATTR_FILTER_PLL_BUCKET to encapsulate BGoffset selection
p9.filter.pll.overlay.scan.initfile
generate correct BGoffset value based on ATTR_FILTER_PLL_BUCKET value
build must process 4x (ATTR values 1..4) to generate set of ring images
p9_xip_customize.C
consume AW keyword from MVPD, set ATTR_FILTER_PLL_BUCKET for HB platform
and customize into SBE image if attribute is present in image
p9_sbe_npll_initf.C
p9_sbe_npll_initf_errors.xml
re-scan perv_pll_bndy ring with selected BGoffset overlay when
ATTR_fILTER_PLL_BUCKET is non-zero
p9_sbe_chiplet_pll_initf.C
p9_sbe_chiplet_pll_initf_errors.xml
adapt to error XML updates in p9_sbe_npll_initf
Change-Id: Id09074d12e95ffc44337e32ec683056d8ec390f3
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49442
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Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com>
Reviewed-by: Sumit Kumar <sumit_kumar@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49460
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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This reverts commit 702e418be9ace793c323710411c2ca6b4d032c58.
Change-Id: Iebbea4e980a974a10a46345262bd475e3e340771
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50800
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Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50802
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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As it is no longer a requirement that Spread Spectrum is enabled on all
SS PLLs in a system in unison, we're better off turning on spreading
as early as possible, so any link training runs off of a spread clock.
The only way to enable Spread Spectrum in P9 is via the TOD Timer, so
we have to set up a timer compare value of 1 and force the TOD value to
1 so that the timer is hit and the TOD's spread enable output turns on.
Change-Id: I0bcd33f17ef06beafb44ba6777d32b98d0680deb
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49662
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Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49667
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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1. align data per FFDC member names
2. set the atomic lock FFDC so that errl parser works
3. collect sibling core data if in fused mode
4. do not collect ffdc on check_master_stop15 fails,
as SBE will do that upon a chip-op request
See https://ralgit01.raleigh.ibm.com/gerrit1/#/c/49473
for FW changes
Change-Id: I9880cdd3480c84c418b662fb7174291ed7b68cdd
RTC: 179364
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50648
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Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50653
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Fix enabling of security in the current power cycle
Change-Id: I546407d90989a876a75b5d36312d31e438024940
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48440
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Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48444
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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p9_sbe_chiplet_reset
remove deassertion of OBUS clk async reset, shift to
p9_sbe_startclock_chiplets
p9_sbe_startclock_chiplets
conditionally remove workaround (assert iovalid, clock, deassert iovalid)
instituted to flush DL glmux select pipeline, these will be set via scan
for supported chips
deassert OBUS clk async reset
p9_chiplet_scominit
remove assertion of NV iovalid from HB
p9.npu.scan.initfile
alter flush state of NVDL glsmux select pipe latches to 0b10
p9.obus.scan.initfile
alter flush state of IOO PHY logic to enable lane clocks
clear RX_LANE_ANA_PDWN
clear RX_CLKDIST_PDWN
set RX_IREF_PDWN_B
Change-Id: Ib9d4bf18a181ed1cf55eaf92e1486c494757d657
CQ: HW404391
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50027
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Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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- Use base addresses vs set addresses to ensure that all fields are correct
cmvc-prereq:1037315
CQ:SW405722
Change-Id: I330c309131ac4ac44c6dc294627e1ff02d33004a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48552
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Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48557
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Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ie7d72d588764e87050b1eded25cc8247b3e99210
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48877
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
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Reviewed-by: Abhishek Agarwal <abagarw8@in.ibm.com>
Reviewed-by: Anusha Reddy Rangareddygari <anusrang@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48880
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I382948a4083293e4ecc42a9759559a060444f5f0
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34997
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
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Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Matt K. Light <mklight@us.ibm.com>
Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35043
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
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checking bits based on pci
osc scenarios
Change-Id: Ida0b6d97cffc1bc43d32dda1f3bdb611e26d56bf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48485
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Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48491
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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* IOF0 pll initf for Axone
* Clock mux settings
Change-Id: I1c6350bca42fc11e8e2a93f4134ea5db76daf79e
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48278
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48282
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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update the metadata to reflect that HWPs
are product ready (HWP Level: 3)
Change-Id: I7199693614997bef5d5b5c9373e20c6c44a05a1a
Original-Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48503
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Using pci_clk_req enum to set
osc0 and osc1 configurations
Change-Id: Ie4a45f121e9c5ecb2e4883332ac948d80ab6a6cf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44218
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48502
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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for osc switch settings
Change-Id: I8279e5f96b79274685ff3bbee4f1eb4d941cfa43
Original-Change-Id: I9e762d2c4b552e84a3a2cc48ec0d9d75732b07cf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41676
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48501
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Also included wrap files
and makefiles
Change-Id: I228028a5af319ebda4343e5cf39b3f2618162470
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23474
Tested-by: Jenkins Server
Dev-Ready: Brent Wieman <bwieman@us.ibm.com>
Reviewed-by: Manish K. Chowdhary <manichow@in.ibm.com>
Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com>
Reviewed-by: Parvathi Rachakonda
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48500
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ibcd2d49f00e6c3488fcbde0d80adf0bdc00b2a97
Original-Change-Id: I3ea0eec08ce479057277524021bfce540d7b63ca
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/17755
Reviewed-by: Brian Silver <bsilver@us.ibm.com>
Tested-by: Brian Silver <bsilver@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48499
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
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There is a phase sync signal between the Nest and MC chiplets that is
only needed for combined synchronous LBIST of the inter-chiplet interface,
but can disrupt scanning in async MC operation. So it should be masked in
normal operation by setting the VITL_AL flag in NET_CTRL0.
Change-Id: Ic051943bbb915081b979078d248bf681c7ca5251
CQ: HW422475
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48055
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Dev-Ready: LENNARD G. STREAT <lstreat@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48057
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Enable TP RIDI in this step for Cronus only, in cache contained mode
Change-Id: I58635087fe6a924db32ada48a34f5df65fc44aa7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47000
Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Dev-Ready: Matt K. Light <mklight@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47006
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: I27f7c75d73881a54152a77c7ab2c8b49be19adb7
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47148
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Juan R. Medina <jrmedina@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/47162
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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p9_sbe_npll_setup used a bad target to clear the PLL unlock indication
(luckily the misguided writes hit benign registers)
p9_hcd_cache_dpll_setup didn't clear the unlock indicator at all
CMVC-Prereq: 1035048
Change-Id: Ia77e8f168e00eba9effb9b3cf0bbb7df2e814749
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45100
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: YUE DU <daviddu@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45102
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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update the metadata to reflect that HWPs
are product ready (HWP Level: 3)
Change-Id: I5a7380e9f34865b3e0ef7872d6338a840b08aa4a
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46789
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46791
Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Previously, we were enabled TP RIDI before we did a bunch of scans which
touch LPC logic. This was causing LPC logic to get messed up because
once TP ridi is enabled LPC traffic is flowing. To get around this,
we are moving the enablement of the TP RIDI to after the scans of the
LPC logic so that the LPC logic wont get messed with
Change-Id: I6244fdf1314a21d9c76519bde3905287c7870b26
CQ: SW396004
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46941
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46966
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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-Relax a restrictive check where the "force" fuse lab
mode bit would cause a FW error even if the part is
in HW fused mode (was just requesting same setting)
-Check still prevents mistaken requests when in
Normal core mode when lab mode can't override
Change-Id: Iad710bceb90bd1bd8d988ba0234c446c63773158
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46292
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com>
Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com>
Reviewed-by: Gregory S. Still <stillgs@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46409
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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Change-Id: Ifce6ec07e888a51ee55f2d53bd884e7fd229c066
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45556
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com>
Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com>
Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com>
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