summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C
Commit message (Expand)AuthorAgeFilesLines
* Streamline the way PIB/NET are initialized between SBE and CronusJoachim Fenkes2019-07-301-9/+53
* p9_sbe_tp_chiplet_init: Fix missing semicolonsJoel Stanley2018-11-011-2/+2
* Axone only-IPL Procedures update to support SBE changesAbhishek Agarwal2018-09-101-26/+102
* Update hardware procedure metadataAnusha Reddy Rangareddygari2017-10-041-1/+1
* p9_sbe_tp_chiplet_init1: Set TP_TCPERV_SRAM_ENABLE_DCJoe Dery2017-06-231-0/+5
* tp/nest reset: add INEX scan type in non-gptr/time/repr scan0 operationJoe Dery2017-03-141-1/+1
* p9_sbe_tp_chiplet_init1 optimizedAnusha Reddy Rangareddygari2017-01-241-26/+22
* p9_sbe_tp_chiplet_init1: Enable PCB automatic reset on timeoutJoachim Fenkes2016-11-041-0/+4
* Update file headersSachin Gupta2016-09-161-1/+1
* SBE move import`Shakeeb2016-09-011-0/+134
OpenPOWER on IntegriCloud