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* RAS_XML: updates to sync the XML with actual values from hardwareZane Shelley2018-09-171-1/+1
| | | | | | | | | | | | | | | | Change-Id: I590d6790cd391ff4be984001acd41c6a1ba48a06 CQ: SW445620 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63398 Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63841 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabledJoe McGill2018-07-181-0/+11
| | | | | | | | | | | | | | | Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Set up oscillator error mask based on MF osc settingJoachim Fenkes2018-07-041-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | On Cumulus, set up the oscerr mask (0102001A) such that errors on unused MF/PCI oscillators are masked (based on the setup in RC3), making sure the corresponding FIR bit (TP LFIR bit 37) will not report false positives. Keep the mask constant for Nimbus as only MF oscillator 0 is in use there. This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5 because a correct mask setting here obviates the need for selective FIR masking. Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask TP LFIR 37 only when MF oscswitch redundancy enabledJoe McGill2018-06-181-3/+12
| | | | | | | | | | | | | | Change-Id: Ib2614f887a3da7801db9d8680520e21daef90fba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60435 Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60443 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* shift OBUS FIR programming inits for secure bootJoe McGill2018-06-171-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_scominit: unmask all OBUS EXTFIR bits, use PB CENT FIR 14 to mark update for downstream code (qualify XBUS/OBUS EXTFIR updates to apply to PPE platform only) p9_fab_iovalid: conditionally unmask OBUS EXTFIR based on state of PB CENT FIR 14 (will handle unmasking here when insecure -- Cronus or old SBE images) p9_obus_extfir_setup: new HWP for HB to call, mask OBUS EXTFIR bits for unused busses Change-Id: I07e7da4a7c61c041451ff4ddfeec3c266385d404 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60361
* p9_sbe_scominit -- unmask TP LFIR bit 37 for CumulusJoe McGill2018-06-081-0/+16
| | | | | | | | | | | | | | | Change-Id: Id216f65d5c240d88c4db62e374c9f3278d623fbb CQ: SW432374 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60118 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/60125 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* move xlink psave configuration to SBEJoe McGill2018-04-031-1/+29
| | | | | | | | | | | | | | | | | | | | | | | 55058 added inits to prime the PPE for xlink psave the register touched is in the blacklist, so it can't be touched on slave chips via FSI in the ioe tl SCOM initifle -- this was triggering HW CI failures this commit simply shifts the register setup into the SBE, where it can be performed securely Change-Id: I57504ccfe4c5f7e71397d11c7468da42ec09f059 CQ: SW421691 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56252 Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/56256 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FIR + RAS XML updatesJoe McGill2018-02-151-2/+2
| | | | | | | | | | | | | | | | | | | p9_sbe_scominit.C mask PBCENT FIR bit 5, rely on action of unit master specific FIR bits to drive attention generation on any cresp address error condition Change-Id: I3c23aeecd426687fe91d37aadfd5ca6243c4a4b3 CQ: SW417475 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54067 Reviewed-by: Daniel J. Henderson <hende@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/54082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* cresp address error handling updatesJoe McGill2018-02-011-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit sets up the FBC trace arrays to stop on a combined response address error, for MPIPL FFDC collection. It also adjusts the FIR configuration for several units, to trigger a system checkstop (based on their own LFIR) if they master a command which recieves a combined response address error cresp, and we do not support MPIPL from that condition. Unlike in past projects, the FBC level cresp address error FIR bit cannot be set to checkstop (in order to support MPIPL scenarios where the unacknowledged access eminates from the core) FIR action bits modified: PSIHB bits 15:20 PBA bit 1 Change-Id: Ie569600c2c937644740636e8a33097f7979d8d6f CQ: SW411054 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52604 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/52634 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* shift XBUS FIR programming inits for secure bootJoe McGill2018-01-261-1/+127
| | | | | | | | | | | | | | | | | | | | | | general approach: - enable runtime FIR settings in SBE code, for all present XBUS regions - remove FIR initialization from HB code which runs prior to SMP build - update HB HWPs to re-mask XBUSes which are present but not functionally used CQ: SW409902 CQ: SW409903 CQ: SW409905 Change-Id: I378ed2ca39c0d5be894420bfc3257e41e3e95de5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50519 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/50528 Reviewed-by: Hostboot Team <hostboot@us.ibm.com>
* MCD disable workaround for HW423589 (option1)Joe McGill2018-01-121-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml add ATTR_CHIP_EC_FEATURE_HW423589_OPTION1, defines set of chips which need MCD disable for HW423589 (applied to Nimbus EC20 and 22+) p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scan.initfile p9.l3.scan.initfile p9.mmu.scom.initfile p9.ncu.scan.initfile p9.npu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_pcie_config.C set unit scope disable dials p9_sbe_scominit.C p9_pm_pba_init.C set PBA unit scope disable dial p9_pm_set_homer_bar.C change PBA0 default command scope from GROUP to NODAL p9.fbc.ab_hp.scom.initfile disable group master setup p9_setup_bars.C p9_setup_bars_defs.H skip MCD setup for HW423589_OPTION1 cmvc-prereq: 1043014 Change-Id: I402701bdd3266e19dbbe8c717b8a54942e3c9ee2 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48961 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48963 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Chip address extension workaround for HW423589 (option2), part1Joe McGill2017-12-011-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | chip_ec_attributes.xml nest_attributes.xml p9_sbe_attributes.xml add ATTR_CHIP_EC_FEATURE_EXTENDED_ADDRESSING_MODE, defines set of chips which physically support the feature add ATTR_CHIP_EC_FEATURE_HW423589_OPTION2, defines set of chips which need extended address workaround for MCD issue (applied only to Nimbus EC 21) add ATTR_MAX_INTERLEAVE_GROUP_SIZE, to restrict maximum size of memory groups formed. Written by p9_mss_eff_grouping. For HW423589_OPTION2, this will default to 512GB add ATTR_FABRIC_ADDR_EXTENSION_[GROUP|CHIP]_ID, to hold extended address configuration. Written by p9_sbe_fabricinit (SBE) and p9_mss_eff_grouping (HB). For HW423589_OPTION2, this will default to 0b0000_111, consuming all chip ID bits for extended addressing. p9_fbc_utils.C p9_fbc_utils.H extend p9_fbc_utils_get_chip_base_address to support address extension, now outputs set of ranges in each msel based on ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID maintain original function for PPE platform which requires knowledge of non-aliased base addresses only, for code size p9_mss_eff_grouping.C p9_mss_eff_grouping_errors.xml set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for HB platform restrict size of groups formed for HW423589_OPTION2 p9_sbe_fabricinit.C set ATTR_FABRIC_ADDR_EXTENSION[GROUP|CHIP]_ID for SBE platform configure FBC/NMMU extended addressing registers p9_setup_bars.C p9_setup_bars_defs.H p9_setup_bars_errors.xml add general purpose support for extended address mode for HW423589_OPTION2, configure static MCD setup p9_hcode_image_defines.H p9_hcode_image_build.C customize SGPE image with address extension configuration to apply p9.cxa.scom.initfile p9.int.scom.initfile p9.l2.scom.initfile p9.l3.scom.initfile p9.ncu.scom.initfile p9.nx.scom.initfile p9.trace.scan.initfile p9.vas.scom.initfile p9_hcd_cache_scominit.C p9_hcd_cache_scominit.c p9_pcie_config.C set unit address extension configuration on supported chips p9_rng_init_phase2.C p9_sbe_scominit.C p9c_set_inband_addr.C p9_sbe_load_bootloader.C p9_sbe_mcs_setup.C adapt to alterations in p9_fbc_utils_get_chip_base_address Change-Id: I614d566c073f1169f04f647057e6e85889f1c237 CQ: HW423589 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48576 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/48892 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- unmask PB EAST FIR 31 for hypervisor TIJoe McGill2017-08-251-1/+1
| | | | | | | | | | | | | | Change-Id: I584450ac1d6190c141db29a8f37d40c05f440c04 CQ: SW396917 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45058 Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/45064 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Create dmi.pll.scan.initfileBen Gass2017-07-141-1/+5
| | | | | | | | | | | | | | | | | | | | Support sync and async mode for Cumulus MC Default buckets are 1. Change-Id: I62d0221abf7f93030cb8c0200a456609ab4dfe04 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40326 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41056 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* RAS XML: masked PBAMFIR[3:4]Zane Shelley2017-06-211-2/+2
| | | | | | | | | | | | | | | Change-Id: Ic5b8d743a4165132c76ea5485d0f01ffe640bea3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/41903 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Benjamin J. Weisenbeck <bweisenb@us.ibm.com> Reviewed-by: Caleb N. Palmer <cnpalmer@us.ibm.com> Reviewed-by: Brian J. Stegmiller <bjs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/42012 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* support chip swap in memory map via FBC XOR mask programmingJoe McGill2017-05-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_sbe_fabricinit.C p9.fbc.ab_hp.scom.initfile set PB_CFG_XLATE_ADDR_TO_ID based on XOR of effective & absolute FBC group/chip ID attribute values, prior to island mode FBC init cleanup register/field constant todos p9_fbc_utils.C parametrize p9_fbc_utils_get_chip_base_address to support calculation of origin address based on: - effective FBC group/chip ID attributes (EFF_FBC_GRP_CHIP_IDS) - effective FBC drawer origin -- effective FBC group ID + chip ID=0 (EFF_FBC_GRP_ID_ONLY) - absolute FBC group/chip ID attributes (ABS_FBC_GRP_CHIP_IDS) p9_sbe_mcs_setup.C (MCS BAR for HB dcbz support) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_ID_ONLY configures BAR address based on drawer base + HRMOR p9_sbe_load_bootloader.C set p9_fbc_utils_get_chip_base_address call for bootloader load to use EFF_FBC_GRP_ID_ONLY (drawer) store XSCOM/LPC BAR into bootloader config data structure in exception vector (based on chip offset) p9_mss_eff_grouping.C (MCS/HTM BARs) p9_pcie_config.C (PCIE MMIO BARs) p9_rng_init_phase2.C / p9_hcode_image_build.C (NX RNG BAR) p9_sbe_scominit.C (XSCOM/LPC BARs) p9_setup_bars.C (MCD, FSP/PSI/NPU/INT MMIO BARs) set p9_fbc_utils_get_chip_base_address call to use EFF_FBC_GRP_CHIP_IDS p9_setup_sbe_config.C p9_sbe_attr_setup.C transmit ATTR_PROC_EFF_FABRIC_[GROUP/CHIP]_ID via scratch6 mailbox p9_xip_customize.C init ATTR_PROC_EFF_FABRIC_[GROUP_CHIP]_ID to zero in image Change-Id: I3f30bc81a986872c2e7f47422b96bf7bf7c59b06 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37261 Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37776 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* L3 update -- p9_sbe_scominitJoe McGill2017-05-251-20/+37
| | | | | | | | | | | | | | | | replace locally defined bit field constants with SCOM address header content add FFDC, code callouts for all errors Change-Id: I41d242a173bef2a3bf7a545ad9878b01a9376768 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40363 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: DHRUVARAJ SUBHASH CHANDRAN <dhruvaraj@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40365 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Setting up nmmu lco targets/min based on valid exsJenny Huynh2017-05-111-1/+51
| | | | | | | | | | | | | | Change-Id: I9e1a0aadae5a43f4ddaab2969cd48900585978b3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40051 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40080 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit: enable nest DTSsGreg Still2017-02-151-0/+14
| | | | | | | | | | | | | | | Change-Id: I3f93669c7810ee6680c35387995fde3fdaf96870 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36169 Reviewed-by: Francesco A. Campisano <campisan@us.ibm.com> Dev-Ready: Francesco A. Campisano <campisan@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/36187 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FIR updates -- pervasive/core/PPEJoe McGill2017-02-021-3/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_obus_scom_address_fixes.H add OBUS IO PPE address constants p9.cme.scan.initfile align EQ pervasive LFIR/XFIR settings with RAS XML docs p9.core.scan.initfile align EC pervasive LFIR/XFIR settings with RAS XML docs p9.core.scom.initfile p9_hcd_core_scominit.c adjust core FIR action settings for bits 1,12:13 to match RAS XML doc p9_sbe_scominit.C mask PBA FIR bit 1 to match RAS XML doc initialize FBC/XBUS/OBUS PPE FIR registers p9_sbe_common.C align non-EQ/EC pervasive LFIR/XFIR settings with RAS XML docs CMVC-prereq:1014393 CMVC-prereq:1014431 Change-Id: Ifbc6a47eb2dbe268a7ea832e55986d46a1870420 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34271 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34336 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Change auto variables to referencesspashabk-in2016-11-221-3/+3
| | | | | | | | | | | | | | | | | Change-Id: I2b9c38757f89d23c627e4a8f2cb3b072bd3bc984 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32867 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32870 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- configure FBC personalization for MC chipletsJoe McGill2016-10-281-7/+7
| | | | | | | | | | | | | | | Change-Id: I3cc772c6a9edc1f060a47ed6160423a3e9f60559 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31911 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31913 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit update for Async MCAbhishek Agarwal2016-10-211-127/+22
| | | | | | | | | | | | | | | Change-Id: I05e9a81ae0afb9261da4a7835ffe281b68f31b0d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30668 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30671 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- invoke NMMU scom initfileJoe McGill2016-10-151-0/+16
| | | | | | | | | | | | | | | | remove from p9_chiplet_scominit Change-Id: Icf1fb69dd663a3fdb1ef160602d930c733a35125 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31286 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31287 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add initfiles for trace default setupJoachim Fenkes2016-09-291-0/+25
| | | | | | | | | | | | | | | | | | | | - Stop trace on xstop+recov for core, cache, nest - Stop trace on xstop for all other chiplets - Synchronous start/stop of nest trace via N3 - Set up fabric compression mask so we're not swamped with bogus entries - Set up PIB trace compression to only look for valid bit Change-Id: I7b983f45784e425cb2ac786cd9da23de7dec682d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29884 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30333 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* FIR updatesJoe McGill2016-09-191-55/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9.cme.scan.initfile add CME LFIR settings add EQ pervasive LFIR/XFIR settings p9.npu.scom.initfile update NPU_0/NPU_1 LFIR settings p9.psi.scom.initfile add PSI LFIR settings p9_sbe_scominit add LPC LFIR settings update placeholder for pervasive LFIR/XFIR settings (for Nest/XBUS/MC/OBUS/PCIE) p9_sbe_tp_chiplet_init3 update TP pervasive LFIR settings p9_pcie_config fix bug affecting PHBBAR programming (causing invalid BAR matches) p9_pcie_scominit update PEC LFIR settings p9_setup_bars_defs update MCD LFIR settings Change-Id: I8aaf7f40e96cde2fbd6e44fd0451e0add6584b77 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29197 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29200 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update file headersSachin Gupta2016-09-161-1/+1
| | | | | | | | Change-Id: Icdd7460d8e3213f9bbd3d52e7825242bc59fc9e9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29825 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SBE move import`Shakeeb2016-09-011-0/+405
Change-Id: I726951318cdb19fd445af2f7910e0d6872eff18c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29086 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
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