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authorJoe McGill <jmcgill@us.ibm.com>2016-09-02 12:24:03 -0500
committerSachin Gupta <sgupta2m@in.ibm.com>2016-09-19 00:38:56 -0400
commitbb215a103af37f8aed69ac9482fca7bfb022a066 (patch)
treed85beb1fc5a6c52069a4eee9e7fd7b9ce33addbb /src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
parentf4763c3a97727a97827b5a09c4cfb55f3276fbe6 (diff)
downloadtalos-sbe-bb215a103af37f8aed69ac9482fca7bfb022a066.tar.gz
talos-sbe-bb215a103af37f8aed69ac9482fca7bfb022a066.zip
FIR updates
p9.cme.scan.initfile add CME LFIR settings add EQ pervasive LFIR/XFIR settings p9.npu.scom.initfile update NPU_0/NPU_1 LFIR settings p9.psi.scom.initfile add PSI LFIR settings p9_sbe_scominit add LPC LFIR settings update placeholder for pervasive LFIR/XFIR settings (for Nest/XBUS/MC/OBUS/PCIE) p9_sbe_tp_chiplet_init3 update TP pervasive LFIR settings p9_pcie_config fix bug affecting PHBBAR programming (causing invalid BAR matches) p9_pcie_scominit update PEC LFIR settings p9_setup_bars_defs update MCD LFIR settings Change-Id: I8aaf7f40e96cde2fbd6e44fd0451e0add6584b77 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29197 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29200 Reviewed-by: Hostboot Team <hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C141
1 files changed, 86 insertions, 55 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
index 3bf2b451..d67f981a 100644
--- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
+++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C
@@ -60,19 +60,24 @@ const uint64_t LPC_BAR_MASK = 0xFF000000FFFFFFFFULL;
// FBC FIR constants
const uint64_t FBC_CENT_FIR_ACTION0 = 0x0000000000000000ULL;
-const uint64_t FBC_CENT_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
-const uint64_t FBC_CENT_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_CENT_FIR_ACTION1 = 0x0440000000000000ULL;
+const uint64_t FBC_CENT_FIR_MASK = 0x111FC00000000000ULL;
const uint64_t FBC_WEST_FIR_ACTION0 = 0x0000000000000000ULL;
-const uint64_t FBC_WEST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
-const uint64_t FBC_WEST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_WEST_FIR_ACTION1 = 0x0000000000000000ULL;
+const uint64_t FBC_WEST_FIR_MASK = 0x0000FFFFC0000000ULL;
const uint64_t FBC_EAST_FIR_ACTION0 = 0x0000000000000000ULL;
-const uint64_t FBC_EAST_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
-const uint64_t FBC_EAST_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t FBC_EAST_FIR_ACTION1 = 0x0000000000000000ULL;
+const uint64_t FBC_EAST_FIR_MASK = 0x00FF1FFFC0000000ULL;
+
+// LPC FIR constants
+const uint64_t LPC_FIR_ACTION0 = 0x0000000000000000ULL;
+const uint64_t LPC_FIR_ACTION1 = 0xFF00000000000000ULL;
+const uint64_t LPC_FIR_MASK = 0x00F0000000000000ULL;
// PBA FIR constants
const uint64_t PBA_FIR_ACTION0 = 0x0000000000000000ULL;
-const uint64_t PBA_FIR_ACTION1 = 0xFFFFFFFFFFFFFFFFULL;
-const uint64_t PBA_FIR_MASK = 0xFFFFFFFFFFFFFFFFULL;
+const uint64_t PBA_FIR_ACTION1 = 0x0C0100600C000000ULL;
+const uint64_t PBA_FIR_MASK = 0x3082448062FC0000ULL;
// chiplet pervasive FIR constants
const uint64_t PERV_LFIR_ACTION0[15] =
@@ -83,8 +88,8 @@ const uint64_t PERV_LFIR_ACTION0[15] =
0x0000000000000000ULL, // N2
0x0000000000000000ULL, // N3
0x0000000000000000ULL, // X
- 0x0000000000000000ULL, // -
- 0x0000000000000000ULL, // -
+ 0x0000000000000000ULL, // MC0
+ 0x0000000000000000ULL, // MC1
0x0000000000000000ULL, // OB0
0x0000000000000000ULL, // OB1
0x0000000000000000ULL, // OB2
@@ -96,60 +101,60 @@ const uint64_t PERV_LFIR_ACTION0[15] =
const uint64_t PERV_LFIR_ACTION1[15] =
{
- 0x0000000000000000ULL, // TP
- 0xFFFFFFFFFFFFFFFFULL, // N0
- 0xFFFFFFFFFFFFFFFFULL, // N1
- 0xFFFFFFFFFFFFFFFFULL, // N2
- 0xFFFFFFFFFFFFFFFFULL, // N3
- 0xFFFFFFFFFFFFFFFFULL, // X
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // OB0
- 0xFFFFFFFFFFFFFFFFULL, // OB1
- 0xFFFFFFFFFFFFFFFFULL, // OB2
- 0xFFFFFFFFFFFFFFFFULL, // OB3
- 0xFFFFFFFFFFFFFFFFULL, // PCI0
- 0xFFFFFFFFFFFFFFFFULL, // PCI1
- 0xFFFFFFFFFFFFFFFFULL // PCI2
+ 0x8000000000000000ULL, // TP
+ 0x8000000000000000ULL, // N0
+ 0x8000000000000000ULL, // N1
+ 0x8000000000000000ULL, // N2
+ 0x8000000000000000ULL, // N3
+ 0x8000000000000000ULL, // X
+ 0x8000000000000000ULL, // MC0
+ 0x8000000000000000ULL, // MC1
+ 0x8000000000000000ULL, // OB0
+ 0x8000000000000000ULL, // OB1
+ 0x8000000000000000ULL, // OB2
+ 0x8000000000000000ULL, // OB3
+ 0x8000000000000000ULL, // PCI0
+ 0x8000000000000000ULL, // PCI1
+ 0x8000000000000000ULL // PCI2
};
const uint64_t PERV_LFIR_MASK[15] =
{
- 0xFFFFFFFFFFFFFFFFULL, // TP
- 0xFFFFFFFFFFFFFFFFULL, // N0
- 0xFFFFFFFFFFFFFFFFULL, // N1
- 0xFFFFFFFFFFFFFFFFULL, // N2
- 0xFFFFFFFFFFFFFFFFULL, // N3
- 0xFFFFFFFFFFFFFFFFULL, // X
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // OB0
- 0xFFFFFFFFFFFFFFFFULL, // OB1
- 0xFFFFFFFFFFFFFFFFULL, // OB2
- 0xFFFFFFFFFFFFFFFFULL, // OB3
- 0xFFFFFFFFFFFFFFFFULL, // PCI0
- 0xFFFFFFFFFFFFFFFFULL, // PCI1
- 0xFFFFFFFFFFFFFFFFULL // PCI2
+ 0xFFFFFFFFFFC00000ULL, // TP
+ 0xFFFFFFFFFFC00000ULL, // N0
+ 0xFFFFFFFFFFC00000ULL, // N1
+ 0xFFFFFFFFFFC00000ULL, // N2
+ 0xFFFFFFFFFFC00000ULL, // N3
+ 0xFFFFFFFFFFC00000ULL, // X
+ 0xFFFFFFFFFFC00000ULL, // MC0
+ 0xFFFFFFFFFFC00000ULL, // MC1
+ 0xFFFFFFFFFFC00000ULL, // OB0
+ 0xFFFFFFFFFFC00000ULL, // OB1
+ 0xFFFFFFFFFFC00000ULL, // OB2
+ 0xFFFFFFFFFFC00000ULL, // OB3
+ 0xFFFFFFFFFFC00000ULL, // PCI0
+ 0xFFFFFFFFFFC00000ULL, // PCI1
+ 0xFFFFFFFFFFC00000ULL // PCI2
};
// chiplet XIR constants
const uint64_t PERV_XFIR_MASK[15] =
{
- 0xFFFFFFFFFFFFFFFFULL, // TP
- 0xFFFFFFFFFFFFFFFFULL, // N0
- 0xFFFFFFFFFFFFFFFFULL, // N1
- 0xFFFFFFFFFFFFFFFFULL, // N2
- 0xFFFFFFFFFFFFFFFFULL, // N3
- 0xFFFFFFFFFFFFFFFFULL, // X
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // -
- 0xFFFFFFFFFFFFFFFFULL, // OB0
- 0xFFFFFFFFFFFFFFFFULL, // OB1
- 0xFFFFFFFFFFFFFFFFULL, // OB2
- 0xFFFFFFFFFFFFFFFFULL, // OB3
- 0xFFFFFFFFFFFFFFFFULL, // PCI0
- 0xFFFFFFFFFFFFFFFFULL, // PCI1
- 0xFFFFFFFFFFFFFFFFULL // PCI2
+ 0x9FFFFFE000000000ULL, // TP
+ 0x2007FFE000000000ULL, // N0
+ 0x201FFFE000000000ULL, // N1
+ 0x200FFFE000000000ULL, // N2
+ 0x000007E000000000ULL, // N3
+ 0x210FFFE000000000ULL, // X
+ 0x20007FE000000000ULL, // MC0
+ 0x20007FE000000000ULL, // MC1
+ 0x29FFFFE000000000ULL, // OB0
+ 0x29FFFFE000000000ULL, // OB1
+ 0x29FFFFE000000000ULL, // OB2
+ 0x29FFFFE000000000ULL, // OB3
+ 0x21FFFFE000000000ULL, // PCI0
+ 0x207FFFE000000000ULL, // PCI1
+ 0x201FFFE000000000ULL // PCI2
};
@@ -346,12 +351,37 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
"Error from putScom (PU_PBAFIRMASK)");
}
+ // configure LPC FIRs
+ {
+ fapi2::buffer<uint64_t> l_scom_data;
+
+ // clear FIR
+ FAPI_DBG("Configuring LPC FIR");
+ l_scom_data = 0;
+ FAPI_TRY(fapi2::putScom(i_target, PU_SYNC_FIR_REG, l_scom_data),
+ "Error from putScom (PU_SYNC_FIR_REG)");
+
+ // configure action/mask
+ l_scom_data = LPC_FIR_ACTION0;
+ FAPI_TRY(fapi2::putScom(i_target, PU_SYNC_FIR_ACTION0_REG, l_scom_data),
+ "Error from putScom (PU_SYNC_FIR_ACTION0_REG)");
+
+ l_scom_data = LPC_FIR_ACTION1;
+ FAPI_TRY(fapi2::putScom(i_target, PU_SYNC_FIR_ACTION1_REG, l_scom_data),
+ "Error from putScom (PU_SYNC_FIR_ACTION1_REG)");
+
+ l_scom_data = LPC_FIR_MASK;
+ FAPI_TRY(fapi2::putScom(i_target, PU_SYNC_FIR_MASK_REG, l_scom_data),
+ "Error from putScom (PU_SYNC_FIR_MASK_REG)");
+ }
+
// configure chiplet pervasive FIRs / XFIRs
{
for (auto l_chplt_target : i_target.getChildren<fapi2::TARGET_TYPE_PERV>
(static_cast<fapi2::TargetFilter>(fapi2::TARGET_FILTER_TP |
fapi2::TARGET_FILTER_ALL_NEST |
fapi2::TARGET_FILTER_XBUS |
+ fapi2::TARGET_FILTER_ALL_MC |
fapi2::TARGET_FILTER_ALL_OBUS |
fapi2::TARGET_FILTER_ALL_PCI),
fapi2::TARGET_STATE_FUNCTIONAL))
@@ -366,6 +396,7 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target)
// PERV LFIR
FAPI_DBG("Configuring PERV LFIR (chiplet ID: %02X)", l_unit_idx + 1);
+
// reset pervasive FIR
l_scom_data = 0;
FAPI_TRY(fapi2::putScom(l_chplt_target, PERV_LOCAL_FIR, l_scom_data),
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