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* SBE Quiesce Implementation for FIFO/PSURaja Das2016-09-301-2/+5
* move C_PPM_SSHSRC setup from p9_hcd_core_scominit to p9_hcd_core_startclocksJoe McGill2016-09-222-3/+6
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-8/+2
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-09-201-1/+133
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2016-09-202-0/+126
* Update file headersSachin Gupta2016-09-1631-31/+31
* p9_hcd_core_scominit -- invoke p9.core.scom.initfileJoe McGill2016-09-111-1/+13
* core_chiplet_reset: SCAN_RATIO set according to ATTR_DPLL_BYPASS: 0=4:1, 1=1:1Joe Dery2016-09-081-1/+21
* SBE move import`Shakeeb2016-09-0133-0/+3541
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