summaryrefslogtreecommitdiffstats
path: root/src/import/chips/p9/procedures/hwp/core/p9_hcd_core_startclocks.C
Commit message (Expand)AuthorAgeFilesLines
* Istep4: procedures upgrade to level3Yue Du2017-07-201-31/+64
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-281-14/+34
* IPL Only: Drop chiplet fence in scomcust instead of startclocksYue Du2017-03-031-2/+5
* IPL/Stop: Assert ABIST_SRAM_MODE_DC to support ABIST RecoveryYue Du2017-02-281-0/+4
* Revert "Hcode: Drop chiplet fence after scominit and scomcust hwp."YUE DU2017-02-091-0/+3
* Hcode: Drop chiplet fence after scominit and scomcust hwp.Yue Du2017-02-061-3/+0
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-01-311-4/+4
* HCODE: Drop TLBIE Quiesce after initfile scan it to 1Yue Du2016-12-201-2/+2
* Istep4: Shouldn't set group_id in cache-contained modeYue Du2016-12-201-7/+11
* STOP Image updatesYue Du2016-11-211-0/+3
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-12/+17
* p9_hcd_core_startclocks -- set CPLT_CONF0 system/group/chip ID fieldsJoe McGill2016-10-261-0/+19
* Istep4: add enable auto special wakeup after core is upYue Du2016-10-261-0/+6
* Core/Initfile: remove cache contained condtions on core-cc/l2 quiescesYue Du2016-10-061-2/+1
* move C_PPM_SSHSRC setup from p9_hcd_core_scominit to p9_hcd_core_startclocksJoe McGill2016-09-221-0/+6
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-8/+2
* Update file headersSachin Gupta2016-09-161-1/+1
* SBE move import`Shakeeb2016-09-011-0/+285
OpenPOWER on IntegriCloud