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talos-sbe
04-16-2019
07-25-2019
master
Blackbird™ SBE sources
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chips
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p9
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procedures
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hwp
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core
/
p9_hcd_core_startclocks.C
Commit message (
Expand
)
Author
Age
Files
Lines
*
Istep4: procedures upgrade to level3
Yue Du
2017-07-20
1
-31
/
+64
*
IPL: Add global checkstop FIR check in Istep4
Yue Du
2017-04-28
1
-14
/
+34
*
IPL Only: Drop chiplet fence in scomcust instead of startclocks
Yue Du
2017-03-03
1
-2
/
+5
*
IPL/Stop: Assert ABIST_SRAM_MODE_DC to support ABIST Recovery
Yue Du
2017-02-28
1
-0
/
+4
*
Revert "Hcode: Drop chiplet fence after scominit and scomcust hwp."
YUE DU
2017-02-09
1
-0
/
+3
*
Hcode: Drop chiplet fence after scominit and scomcust hwp.
Yue Du
2017-02-06
1
-3
/
+0
*
Istep4: clean up istep4 todo items and mark them with RTC
Yue Du
2017-01-31
1
-4
/
+4
*
HCODE: Drop TLBIE Quiesce after initfile scan it to 1
Yue Du
2016-12-20
1
-2
/
+2
*
Istep4: Shouldn't set group_id in cache-contained mode
Yue Du
2016-12-20
1
-7
/
+11
*
STOP Image updates
Yue Du
2016-11-21
1
-0
/
+3
*
Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setup
Yue Du
2016-11-21
1
-12
/
+17
*
p9_hcd_core_startclocks -- set CPLT_CONF0 system/group/chip ID fields
Joe McGill
2016-10-26
1
-0
/
+19
*
Istep4: add enable auto special wakeup after core is up
Yue Du
2016-10-26
1
-0
/
+6
*
Core/Initfile: remove cache contained condtions on core-cc/l2 quiesces
Yue Du
2016-10-06
1
-2
/
+1
*
move C_PPM_SSHSRC setup from p9_hcd_core_scominit to p9_hcd_core_startclocks
Joe McGill
2016-09-22
1
-0
/
+6
*
Changing ATTR_PG from 32 to 16 bit
Anusha Reddy Rangareddygari
2016-09-21
1
-8
/
+2
*
Update file headers
Sachin Gupta
2016-09-16
1
-1
/
+1
*
SBE move import`
Shakeeb
2016-09-01
1
-0
/
+285