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path: root/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_startclocks.C
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* Istep4: procedures upgrade to level3Yue Du2017-07-201-31/+64
* IPL: Add global checkstop FIR check in Istep4Yue Du2017-04-281-8/+28
* HW405243/IPL: Assert/drop pcb_mux_disable around quad power offYue Du2017-03-311-0/+18
* IPL Only: Drop chiplet fence in scomcust instead of startclocksYue Du2017-03-031-6/+0
* HB/IPL: ex_is_abomination workaround for hostbootYue Du2017-02-101-4/+19
* Revert "Hcode: Drop chiplet fence after scominit and scomcust hwp."YUE DU2017-02-091-0/+6
* Hcode: Drop chiplet fence after scominit and scomcust hwp.Yue Du2017-02-061-6/+0
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-01-311-3/+3
* HW396520: DD1 workaround skip flushmode inhibit drop in cache hwpYue Du2016-12-201-7/+13
* Istep4: Shouldn't set group_id in cache-contained modeYue Du2016-12-201-7/+11
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-2/+2
* HB: fix HB core boot resulting cme bootYue Du2016-11-101-0/+15
* Changing ATTR_PG from 32 to 16 bitAnusha Reddy Rangareddygari2016-09-211-4/+1
* Update file headersSachin Gupta2016-09-161-1/+1
* SBE move import`Shakeeb2016-09-011-0/+334
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