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path: root/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C
Commit message (Expand)AuthorAgeFilesLines
* Revert PLL unlock commits of 45102 and 46563Yue Du2017-10-051-3/+0
* {nest,cache}_pll_setup: Properly clear PLL unlock indicationJoachim Fenkes2017-10-041-0/+6
* STOP: Fix MPIPL Dpll Lock via ensuring mode 1Yue Du2017-09-271-1/+9
* Istep4: procedures upgrade to level3Yue Du2017-07-201-22/+41
* HW404292: Assert analog fence in cache_chiplet_resetYue Du2017-03-311-1/+4
* Istep4: clean up istep4 todo items and mark them with RTCYue Du2017-01-311-12/+4
* Istep4: Enable poll for DPLL lock in p9_hcd_cache_dpll_setupYue Du2016-11-211-11/+26
* PLL configuration updates -- permit e2e bypass executionJoe McGill2016-09-061-28/+43
* SBE move import`Shakeeb2016-09-011-0/+206
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