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* P9-XIP: cleaning up endianess conversionMartin Peschke2016-06-092-149/+54
| | | | | | | | | | | | | | Use system header endian.h routines to do endianess conversion instead of own routines. Change-Id: I6dd657b77b61a9a56797a254af6464f8526cc60f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24893 Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
* HW Image: no .overrides sectionMartin Peschke2016-06-092-12/+2
| | | | | | | | | | | | | | Removing .overrides from HW image since that is going to be a separate PNOR section. Change-Id: Id5fd18390e757be20ae35e484f47a953368f288b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24832 Tested-by: PPE CI Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
* Initial check in of p9_xip_tool.C which supports dissecting ringClaus Michael Olsen2016-06-091-0/+2439
| | | | | | | | | | | | | sections. - Updated xip_tool.C to split dissectRingSection() into an XIP part and an TOR part. Change-Id: I19e5656cea9b7fd02e4972880b3ffff947705047 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24268 Tested-by: PPE CI Tested-by: Jenkins Server Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com>
* Fix include of plat_target_filter.H in target_types.HMike Baiocchi2016-06-081-1/+1
| | | | | | | | | | | | | Change-Id: Ia2309f04e4511cc9cb8730d32c62fec554be16ad Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25406 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Richard J. Knight <rjknight@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25459 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Changes in ecc data fixing so reading and writing worksCHRISTINA L. GRAVES2016-06-087-27/+45
| | | | | | | | | | | | | Change-Id: I8ec5fc295d0e80af6d28f53ed469a3c98450f4df Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24554 Tested-by: Jenkins Server Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24557 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 Procedure for p9_hcd_cache_dcc_skewadjust_setupSoma BhanuTej2016-06-081-0/+8
| | | | | | | | | | | Change-Id: Ifc81c6ae881c7a2ff188f223d15f499f1d518305 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25292 Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Tested-by: Jenkins Server Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25436 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* add core/cache initfilesJoe McGill2016-06-081-3/+20
| | | | | | | | | | | | | | | | | | | | Add SCAN/SCOM initfiles for core/core common/CME/L2/L3/NCU Update initf procedures to call generated SCAN HWPs directly Use for Cronus only testing of initfiles prior to scan via image support Add SCOM initfiles, do not invoke yet to stage PPE commits Change-Id: Ia25c89d784fdf49bc81921c8662123347747d19a Original-Change-Id: I5b65ea980586a3cd0a4c0c0180473dec78234cba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23910 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25382 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update bit-field of TargetFilter enum to match Pervasive NumberingMike Baiocchi2016-06-081-46/+53
| | | | | | | | | | | | | | | | | | | | This moves the bit-field numbering of the TargetFilter enum to a new plat_target_filter.H file. The plat_target_filter.H file added to this commit has the same numbering scheme of what was originally in target_types.H. Change-Id: Ib2fd08abc8a52481ffd00126a13287a29138e55b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24862 Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: Christian R. Geddes <crgeddes@us.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24864 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add memdiags implementation for superfast operationsBrian Silver2016-06-081-0/+3
| | | | | | | | | | | | | | | | Change the actions to repair test fails. Change the translation test to repair fails. Change-Id: I3c6c0a02efce5cb6562fba0f4cda5487eeb79f32 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25168 Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25169 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable New istepsSachin Gupta2016-06-081-1/+0
| | | | | | | | | Change-Id: I4fd808eebf9c9bddf8162811e82017a0ba4c5e3c RTC: 148465 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25115 Tested-by: Jenkins Server Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
* Level 2 HWP for p9_sbe_tp_switch_gearsAnusha Reddy Rangareddygari2016-06-082-6/+13
| | | | | | | | | | | | Change-Id: Ie19e224c45227ae9c4e2edb55352e5933aef64b3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25224 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25227 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-06-081-363/+266
| | | | | | | | | | | | Change-Id: Ib900caeeda41ecaf4dbe7321d7243b247501b5e6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25218 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25220 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* New Attribute for PIBMEM RepairSunil.Kumar2016-06-082-0/+41
| | | | | | | | | | | | | Change-Id: Ifdce0e7a538356c1f0f3bdcd382dd8147167db43 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25225 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25226 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix TODOs in p9_build_smp HWPThi Tran2016-06-082-30/+9
| | | | | | | | | | | | | Change-Id: Iae1cb914a76cf09bc62b8196d0bbf8d6d7181bce RTC:147511 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25209 Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25210 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add attribute file for cache-contained specific behaviorJoe McGill2016-06-081-0/+46
| | | | | | | | | | | | | | | | | ATTR_RUNN_MODE -> System level flag to indicate whether clock start should be achieved by RUNN or normal free-run methods ATTR_RUNN_CYCLE_COUNT -> EQ specific parameter to provide cycle count in case of RUNN start Change-Id: I843249d842b72489f036677a94f5b796d48086bf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23397 Dev-Ready: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Brent Wieman <bwieman@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25286 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_ringId.H: resolve duplicate copies of fileMartin Peschke2016-06-081-248/+0
| | | | | | | | | | | | | | | | | | | | | | As agreed with Prasad, the copy in chips/p9/utils is being abandoned, while the copy in chips/p9/utils/imageProcs is maintained. Both copies have diverged considerably. It looks like the removed copy has never been updated. So I am assuming that there is no code inside the removed copy that needs to be kept and copied over into the retained copy. Change-Id: Ie8b95842c07a44ea273764fad3186db279dc1a3d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24802 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Claus M. Olsen <cmolsen@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: GIRISANKAR PAULRAJ <gpaulraj@in.ibm.com> Tested-by: Hostboot CI Reviewed-by: Martin Peschke <mpeschke@de.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24803 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Translate logical mca regisers in mcs chiplet as mca target typeBen Gass2016-06-081-0/+5
| | | | | | | | | | | | | | | | | Fixup memory code which uses the xlt registers Add dependent epsilon inits Change-Id: I995bcd895a0a7a431dcf350475fd387be70749c9 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24733 Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Dev-Ready: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24945 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_psi_init -- adjust iovalid control, fix todosJoe McGill2016-06-081-1/+23
| | | | | | | | | | | | | | | | | PSI iovalid moved from XBUS->N2 Use field constants from SCOM address header files Use Cronus product APIs to discover active links Change-Id: I0ec0162689b57332315c3765d73312fd4b909802 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25140 Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25185 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2016-06-089-477/+445
| | | | | | | | | | | | | Change-Id: Ife07787240042354d7072f5c4674b14318cb0a71 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25116 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25150 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_block_wakeup_intr Level 2 - fix PPE compilation issueGreg Still2016-06-082-3/+9
| | | | | | | | | | | | | | - Moved ATTR_CHIP_UNIT_POS from core to perv - Add p9_hcd_common.H to allow for Hostboot CI Change-Id: I541f11e7312556a9a2f94226b90fd3b04ce83177 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24401 Tested-by: Hostboot CI Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24461
* p9_block_wakeup_intr Level 2Greg Still2016-06-081-37/+87
| | | | | | | | | | | | | | | | | | | | | | | | | | - Fixed problems with Cronus to ungate testing - Ran on Awan and SUET - Wrapper has ability to just to -set and -clear but also tests all supported options - Added a "no special wakeup" option (parm) has there may be use cases with it as P8 did NOT perform Special Wake-up to set the bit while P9 Hcode is stating this requirement. - Has a placeholder for special wakeup inclusion later. - Address Gerrit comments (round 2) - Rebased (4) Change-Id: I9603f3bf9075eb47636fd78ee474f78c82e87390 Original-Change-Id: I0722065ce59a2c6ebfdc6c8cf77cb5746c3db7aa RTC: 136783 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23347 Tested-by: Jenkins Server Tested-by: Auto Mirror Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24369 Tested-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update makefile for new procedures.Sachin Gupta2016-06-081-0/+2
| | | | | | | Change-Id: I3d850b647b7e388136b477a2c72fb771e764ffcf Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25114 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2016-06-082-0/+131
| | | | | | | | | | | | Change-Id: I8c1e08f5db655db54a91bb0ab4dab91b83f2eaef Original-Change-Id: I707a936f8124f997c338ce01db205b958716a8da Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21489 Tested-by: Jenkins Server Tested-by: Hostboot CI Tested-by: PPE CI Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25113 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-06-082-0/+101
| | | | | | | | | | Change-Id: Ie1c3e381437a35a1e588165ad451137110c2ae8e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23398 Tested-by: Jenkins Server Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25112
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-06-084-77/+243
| | | | | | | | | | | | | Change-Id: Ibf4d7f4e08b925160652f029f673d9392c5cbaef Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24962 Tested-by: Hostboot CI Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24964 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Variable buffer problemsRichard J. Knight2016-06-081-16/+5
| | | | | | | | | | | | | Change-Id: I19eba345844ff3344939f77ec7e7fe8183e1b9a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24725 Tested-by: Jenkins Server Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24727 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Procedure crashes when trying to query an EC featureRichard J. Knight2016-06-081-58/+0
| | | | | | | | | | | | | | | | | | | | -Updated queryEcFeature to have two parts, base attribute reading is now in a library, while feature checking logic is now in small individual inline functions. Change-Id: I4c3685d6a85946297af31f7f3da4d918bca88039 RTC:151184 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23025 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23030 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* remove old Target::getOtherEnd() methodMatt K. Light2016-06-082-29/+0
| | | | | | | | | | | | | Change-Id: I8fc759b33cbc20dbbe1d569b202a59e8258fe394 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24760 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com> Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24761 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2016-06-083-5/+30
| | | | | | | | | | | | | | | | | | | | | default PCB slave hang timer 6 to value appropriate for all sim ratios handle PCB master timeout enable/disable in sim only HWPs use ring caching to limit physical scans performed qualify PCI PLL fastlock updates by perv target state add XBUS CU PLL inits qualify MEM PLL init by sync_mode Change-Id: Ib884a1b73b8be7f99cfa0899613652406db95dbc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24433 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Michael S. Floyd <mfloyd@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24485 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Changes in error handling to stop the read/write as soon as an error occursCHRISTINA L. GRAVES2016-06-082-3/+5
| | | | | | | | | | | | Change-Id: I9a9ee05840f8e22d4e0f4a104434764eba84e8c3 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24376 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24378 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2016-06-082-9/+8
| | | | | | | | | | | | Change-Id: I2343dcaad657640258bcdf7954a9b5702a1061aa Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24885 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24886 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* ADU SupportRaja Das2016-06-083-1/+4
| | | | | | | | | Change-Id: I8351391d75fcd0d8d07e94d2e3378d052993c3a7 RTC: Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22855 Tested-by: Jenkins Server Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
* Update RAM procedures.LiuYangFan2016-06-083-157/+521
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changes included: p9_ram_core: 1. Add special case support for get/put NIA/MSR/CR/FPSCR 2. Add thread stop state check in setup 3. Add error handling when ram_setup/get_reg/put_reg p9_ram_get_all_reg/p9_ram_put_all_reg: Add get/put all registers function for test p9_ram_spr_test: New file to test SPR, verify with SPY read, for Cronus use p9_ram_after_checkstop: New file to test ram after checkstop p9_ram_addr_error_test: New file to test ram after bad address access p9_ram_wrap: Update to support the new tests Change-Id: Ia4da55eae26e9f3a667446bc984b358c064fdd8a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22746 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22747 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Update ekb version of plat_error_scope.H to match new hostboot versionRichard J. Knight2016-06-081-3/+3
| | | | | | | | | | | | | | -fixed FAPI_ASSERT_NOEXIT macro so that it commits error by default Change-Id: I036bd84d8a7f60282ead67a4f160e0898c42d055 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24834 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24837 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_pm_occ_control Fix OCC memory boot launchingGreg Still2016-06-081-1/+32
| | | | | | | | | | | | | | | | | | | - Build and push launcher instructions into OCC SRAM - Set SRAM Boot Vector 3 (FFFF_FFFC) to branch to launcher - Per OCC team, offset is HOMER+0x40 Change-Id: I2abbfea8de7b18d6010ee336031d0867cf9f0e99 RTC: 150818 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23561 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23562 Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Initial check in of xip_tool changes needed to support anotherClaus Michael Olsen2016-06-082-2643/+3
| | | | | | | | | | | | initial check in p9_xip_tool.C Change-Id: I5c2be359f18424b3de90643d1d8ff544573b857f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23801 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23803 Reviewed-by: Martin Peschke <mpeschke@de.ibm.com>
* Level 2 HWP for p9_set_fsi_gp_shadowAnusha Reddy Rangareddygari2016-06-082-1/+133
| | | | | | | | | | | | | Change-Id: Icb0bd70104ce8659a8e22aaca21864caf69846ff Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24796 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24798 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Define attributes for synchronous modeDan Crowell2016-05-201-1/+1
| | | | | | | | | | | | | | | | Changed ATTR_MC_SYNC_MODE to be writeable instead of platInit ATTR_REQUIRED_SYNCH_MODE holds the rules on what mode to use Change-Id: Ibb8b01635db885490e4c4d287e0316bb2e9abffc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24547 Tested-by: Hostboot CI Reviewed-by: ANDRE A. MARIN <aamarin@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24638 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-05-203-2/+29
| | | | | | | | | | | | | Change-Id: Ic5e6400f55cf200c89b9af2cf78074416609734b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24763 Tested-by: PPE CI Tested-by: Jenkins Server Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Tested-by: Hostboot CI Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24765 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* ADU: Support PMISC NHTM control operationsThi Tran2016-05-202-14/+42
| | | | | | | | | | | | Change-Id: Ife477914e9343ff70e7088c51fbd3a3ecde09167 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24682 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: CHRISTINA L. GRAVES <clgraves@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24683 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add MVPD_KEYWORD_FIRST and MVPD_RECORD_FIRST to mvpd defscrgeddes2016-05-201-0/+2
| | | | | | | | | | | | | | | | These enum values help with test cases. Change-Id: I56db6d5221b6d3dd07c0da15b94bcce8ccbcad2b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24618 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24620 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Changes related to packaging of memory vpd on Nimbuswhs2016-05-203-18/+21
| | | | | | | | | | | | | | | | | | Create a HWP to process MR and MT keyword to map to memory vpd keyword. Change specialization from MCS to MCA. Change-Id: I426e4c7600e2158737c82e3c2380518c392ada5b RTC: 144519 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23775 Tested-by: Jenkins Server Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23797 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_switch_gears -- skip i2c access outside of SBE platformJoe McGill2016-05-201-10/+3
| | | | | | | | | | | | | | | | | additional updates after review with Srinivas/Soma remove clearing of PERV_CTRL0_SET_TP_PLLBYP_DC (covered in p9_sbe_npll_setup) guard all i2c setup code to apply to SBE only will execute in Cronus platform (forthcoming p9_sbe_clock_test2 code) Change-Id: I1884128a074fbd5c587d7867f03c71ed719de80e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24572 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24573 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.core.common.initfile -- clear PSSCR[RL] for cache contained modeJoe McGill2016-05-201-1/+1
| | | | | | | | | | Change-Id: If439ff3fe4432739b763dd16f45312fc3f590135 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24515 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24520 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_pm_corequad_init: Level 2 - Fapi 1.0 to Fapi 2.0 transliterationSangeetha T S2016-05-201-0/+2350
| | | | | | | | | | | | | | Change-Id: I779ac5c24decb6121ce8a4e7a46ea657d0cbf3d7 RTC: 148006 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22233 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22234 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix assert() in variable_bufferRichard J. Knight2016-05-201-3/+7
| | | | | | | | | | | | | | | | -Updated code to use fapi2::Assert instead of assert() Change-Id: I5184f1f41c7b0568fac8d98e6b38d4de1b76269f RTC:128525 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24261 Tested-by: Jenkins Server Reviewed-by: Matt K. Light <mklight@us.ibm.com> Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24263 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* add Target::isFunctional()Matt K. Light2016-05-192-0/+22
| | | | | | | | | | | | | | | | | | | -PPE and Cronus would like to check if a target is functional using different attributes. This method would abstract the checking. PPE would use ATTR_PG_* Cronus would use ATTR_FUNCTIONAL Change-Id: I59710cd118f756bed676fb94c38bbf0517f24730 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24721 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Brian R. Silver <bsilver@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Santosh S. Puranik <santosh.puranik@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24722
* Updated attribute valuesSoma BhanuTej2016-05-171-1/+1
| | | | | | | | | | | | | | I2C_Rate, boot_flags and RISK_LVL Change-Id: I99a9a7260fc985accc09d20a90420728bebe7d23 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24644 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Sunil Kumar <skumar8j@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24645 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Level 2 HWP for p9_sbe_attr_setup,p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-166-57/+154
| | | | | | | | | | | | | | Change-Id: Ib3c07a029d28c4923b2e8dee32bd8067a13d67a5 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24365 Tested-by: Jenkins Server Tested-by: PPE CI Tested-by: Hostboot CI Reviewed-by: Soma Bhanutej <soma.bhanu@in.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Sangeetha T S <sangeet2@in.ibm.com> Reviewed-by: PARVATHI RACHAKONDA <prachako@in.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24413 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* add core/cache initfilesJoe McGill2016-05-161-6/+66
| | | | | | | | | | | | | | | | | | | | Add SCAN/SCOM initfiles for core/core common/CME/L2/L3/NCU Update initf procedures to call generated SCAN HWPs directly Use for Cronus only testing of initfiles prior to scan via image support Add SCOM initfiles, do not invoke yet to stage PPE commits Change-Id: I816e583363d7b547cec483de9a8db9f5d3b2e607 Original-Change-Id: I5b65ea980586a3cd0a4c0c0180473dec78234cba Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23910 Tested-by: Jenkins Server Tested-by: PPE CI Reviewed-by: Benjamin Gass <bgass@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24519 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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