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* Remove duplicate set of fabric topology attributesJoe McGill2016-01-213-34/+7
* Power Management Platform and Frequency AttributesGreg Still2016-01-211-20/+0
* Fix for mirroingSachin Gupta2016-01-212-1/+1
* Level 2 HWP for p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2016-01-211-0/+31
* P9-XIP image build: initial implementationMartin Peschke2016-01-219-0/+8254
* p9_pm_pfet_init Level 2Amit Kumar2016-01-211-2/+56
* Fix all incorrect copyright prologsStephen Cprek2016-01-211-1/+1
* Power Management Platform and Frequency AttributesGreg Still2016-01-211-0/+812
* New scom addresses const headers for chip 9031Ben Gass2016-01-191-591/+501
* Fix all incorrect copyright prologsStephen Cprek2016-01-191-1/+1
* Intermediate updates for header files.Ben Gass2016-01-191-626/+3
* Regenerated header files from e9029Ben Gass2016-01-192-2366/+6177
* Generated from n10_e9024_tp023_spider_u223_01Ben Gass2016-01-192-0/+12460
* Compilation issue fixSachin Gupta2015-12-211-1/+1
* Solve unused label compilation issue in sbeSachin Gupta2015-12-211-1/+1
* Add values to CHIP_UNIT_POS for all pervasive chipletsSantosh Puranik2015-12-091-1/+30
* Makefile InfraSunil.Kumar2015-12-0811-0/+333
* Make OB1,OB2 (cumulus only) non-functionalSachin Gupta2015-12-081-2/+2
* Action file for SBE HWPSunil.Kumar2015-12-081-0/+145
* p9_adu_access and p9_adu_setup L2 proceduresCHRISTINA L. GRAVES2015-12-081-0/+91
* JET: Level 2, Make p9_pm_occ_control FAPI2.0 compilantSangeetha T S2015-12-081-3/+15
* Suet.scomdef and chip.actMichael Dye2015-12-081-0/+18
* JET: SUET updates for p9_hcd_cache_startclocks and p9_hcd_core_startclocksSangeetha T S2015-12-081-0/+39
* Refactor Suet Data File StructureBill Hoffa2015-12-083-0/+3
* Entries for p9_sbe_load_bootloaderSunil.Kumar2015-12-041-1/+8
* Avoid hash collision in ppe.Sachin Gupta2015-12-041-1/+1
* Checking in the L2 p9_sbe_load_bootloader proceduresCHRISTINA L. GRAVES2015-12-011-0/+47
* Changing data inputs from 64 to 8-bit array and adding firstGranuleCHRISTINA L. GRAVES2015-12-011-1/+1
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2015-12-011-2/+0
* Checking in the L2 p9_sbe_load_bootloader proceduresCHRISTINA L. GRAVES2015-12-012-0/+142
* Shift HWP content to align with desired EKB layoutJoe McGill2015-12-013-0/+333
* Changing data inputs from 64 to 8-bit array and adding firstGranuleCHRISTINA L. GRAVES2015-11-254-17/+31
* Attribute Xml required for ppe RepoSunil.Kumar2015-11-251-0/+55
* Changing data inputs from 64 to 8-bit array and adding firstGranuleCHRISTINA L. GRAVES2015-11-251-2/+6
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2015-11-251-35/+16
* FBC Level 1 proceduresJoe McGill2015-11-251-1/+1
* Checking in the L2 p9_sbe_load_bootloader proceduresCHRISTINA L. GRAVES2015-11-251-0/+168
* Shift HWP content to align with desired EKB layoutJoe McGill2015-11-252-0/+636
* Adding target for lco_m, changed flags, changed INF to DBGCHRISTINA L. GRAVES2015-11-201-4/+12
* Checking in the L2 p9_pba_access and p9_pba_setup proceduresCHRISTINA L. GRAVES2015-11-201-0/+60
* Changing address because of fix in the new modelCHRISTINA L. GRAVES2015-11-201-3/+1
* Adding target for lco_m, changed flags, changed INF to DBGCHRISTINA L. GRAVES2015-11-206-227/+218
* Shift HWP content to align with desired EKB layoutJoe McGill2015-11-207-0/+1057
* Fix for ppe compilatoin errorSunil.Kumar2015-11-203-41/+131
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2015-11-192-0/+120
* Regenerated header files from e9029Ben Gass2015-11-195-31917/+55297
* Updates for p9_revert_sbe_mcs_setup, p9_sbe_mcs_setup (Level 2)Joe McGill2015-11-193-59/+194
* PPE-HWP: [Level 2] Cache/Core chiplet_reset/init/scan0+startclocksYue Du2015-11-1928-948/+639
* p9_sbe_setup_boot_freq Level 2 - Setup boot frequencySudheendra K Srivathsa2015-11-191-0/+10
* Level 2 HWP p9_sbe_tp_chiplet_init3.CSunil.Kumar2015-11-191-24/+19
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