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* Update prologs of mirrored files to have apache licenseStephen Cprek2016-08-15248-1864/+3622
* Fapi delay updatesAnusha Reddy Rangareddygari2016-08-121-6/+8
* p9_sbe_chiplet_reset: Change NX_1 hang pulse period to 68sJoachim Fenkes2016-08-112-2/+3
* Procedures modified for DD1 changesSunil.Kumar2016-08-115-5/+60
* p9_sbe_tp_chiplet_init3 updatesAnusha Reddy Rangareddygari2016-08-111-3/+3
* Attibutes modified for 9067 model.Sunil.Kumar2016-08-111-5/+5
* p9_sbe_scominit_errors.xml -- add empty file to establish PPE mirrorJoe McGill2016-08-111-0/+21
* p9_ring_id.h: move ring IDs to plain C header fileMartin Peschke2016-08-096-6/+6
* OCC Special Timeout handlingSangeetha T S2016-08-041-0/+14
* p9_pm_init: Level 2: Implement functionalitySangeetha T S2016-08-041-26/+28
* FAPI_INF entering and exiting message updatesAnusha Reddy Rangareddygari2016-08-0427-172/+172
* scan HWP updatesJoe McGill2016-08-047-200/+380
* Add sbeError tag to all SBE related error xml filesRichard J. Knight2016-08-0326-9/+107
* fix logic setting ATTR_PROC_SBE_MASTER_CHIPJoe McGill2016-08-011-7/+8
* scan HWP updatesJoe McGill2016-08-017-59/+92
* add values for ATTR_DPLL_VDM_RESPONSE enumerationsJoe McGill2016-08-011-4/+4
* CORE/CACHE: core/cache/l2_stopclocks Level 2Yue Du2016-07-291-0/+8
* Improve ATTR_PGDan Crowell2016-07-291-1/+6
* Adding in writing to HRMOR for bootloaderCHRISTINA L. GRAVES2016-07-265-4/+90
* Modify #V accessor function for new version 3Andres Lugo-Reyes2016-07-261-1/+1
* CORE/CACHE: remove runinit procedures.Yue Du2016-07-266-252/+0
* Pstate Parameter Block structureGreg Still2016-07-233-187/+640
* Level 2 HWP for p9_hcd_cache_dcc_skewadjust_setupAnusha Reddy Rangareddygari2016-07-231-5/+74
* Level 2 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-07-214-5/+50
* p9_sbe_fabricinit -- change scope of pbop commandJoe McGill2016-07-201-1/+6
* Fapi delay updatesAnusha Reddy Rangareddygari2016-07-202-2/+2
* VBU IPL -- update sim PLL configurationJoe McGill2016-07-205-93/+94
* p9_dump_stop_info.C - Level 1Greg Still2016-07-191-1/+24
* Level2 HWP for p9_check_chiplet_statesAbhishek Agarwal2016-07-192-16/+7
* p9_sbe_select_ex Level 2 updateGreg Still2016-07-192-220/+353
* Fix paranthesis syntax in scom initfilesPrachi Gupta2016-07-183-30/+30
* Adding in a delay between ADU reads for fastmode and looping aroundCHRISTINA L. GRAVES2016-07-181-80/+82
* process SBE NPLL/chiplet PLL error filesJoe McGill2016-07-141-0/+2
* add empty error files for SBE PLL initf procedures to setup mirrorJoe McGill2016-07-142-0/+42
* Level 2 HWP for p9_hcd_ccahe_dcc_skewadjust_setupAnusha Reddy Rangareddygari2016-07-121-2/+2
* Level 2 HWP p9_sbe_nest_initfSunil.Kumar2016-07-122-25/+76
* Level 2 HWP To scan gptr repr time ringsSunil.Kumar2016-07-124-13/+243
* Update for p9_sbe_npll_initfSunil.Kumar2016-07-121-1/+1
* Level 2 HWP for p9_sbe_attr_setupAnusha Reddy Rangareddygari2016-07-121-3/+17
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-07-112-8/+158
* attributes: use ATTR_BOOT_FREQ_MULT (drop FMULT), fix VBU sc/mc EP03 ATTR_PGJoe Dery2016-07-114-18/+5
* Add ATTR_PG to SBE attributesSantosh Puranik2016-07-111-231/+96
* Use ATTR_PG attributeSantosh Puranik2016-07-081-680/+0
* p9_sbe_chiplet_reset Level 2 update: set EC/core multicast reg3=group3Joe Dery2016-07-082-24/+35
* Level 2 HWP p9_sbe_io_initfSunil.Kumar2016-07-081-7/+74
* CORE/CACHE: add Level1 cache/l2/core stopclocks proceduresYue Du2016-07-081-10/+25
* CORE/CACHE: fix initf procedures on ring IDs and ex partial goodYue Du2016-07-085-39/+54
* HWP Level 2 p9sbe_tp_initfSunil.Kumar2016-07-081-13/+16
* Level2 HWP p9_sbe_npll_initfSunil.Kumar2016-07-071-31/+32
* Level1 HWP for p9_check_chiplet_statesAbhishek Agarwal2016-07-072-0/+39
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