summaryrefslogtreecommitdiffstats
path: root/import/chips/p9/procedures/hwp
Commit message (Expand)AuthorAgeFilesLines
* Level 2 HWP for p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-06-171-3/+6
* Move prevasive procedures to SEEPROMSachin Gupta2016-06-154-3/+16
* Update p9_l2_scom.C to sync with latest p9.l2.scom.initfilePrachi Gupta2016-06-131-0/+8
* Changes in ecc data fixing so reading and writing worksCHRISTINA L. GRAVES2016-06-087-27/+45
* add core/cache initfilesJoe McGill2016-06-081-3/+20
* Enable New istepsSachin Gupta2016-06-081-1/+0
* Level 2 HWP for p9_sbe_tp_switch_gearsAnusha Reddy Rangareddygari2016-06-082-6/+13
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-06-081-363/+266
* Fix TODOs in p9_build_smp HWPThi Tran2016-06-082-30/+9
* Level 2 HWP for p9_sbe_nest_startclocks,p9_sbe_startclock_chipletsAnusha Reddy Rangareddygari2016-06-084-443/+406
* p9_block_wakeup_intr Level 2 - fix PPE compilation issueGreg Still2016-06-082-3/+9
* p9_block_wakeup_intr Level 2Greg Still2016-06-081-37/+87
* Update makefile for new procedures.Sachin Gupta2016-06-081-0/+2
* HWP-CACHE/CORE:istep4 procedures updatesYue Du2016-06-082-0/+131
* Level 1 HWP for p9_hcd_cache_chiplet_l3_dcc_setupAnusha Reddy Rangareddygari2016-06-082-0/+101
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-06-082-77/+221
* partial good/hang pulse updates to support all sim models/clock ratiosJoe McGill2016-06-083-5/+30
* Changes in error handling to stop the read/write as soon as an error occursCHRISTINA L. GRAVES2016-06-082-3/+5
* Adding in LPC functional reset to sbe_lpc_initCHRISTINA L. GRAVES2016-06-082-9/+8
* ADU SupportRaja Das2016-06-082-1/+3
* Update RAM procedures.LiuYangFan2016-06-082-148/+513
* p9_pm_occ_control Fix OCC memory boot launchingGreg Still2016-06-081-1/+32
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-05-201-2/+18
* ADU: Support PMISC NHTM control operationsThi Tran2016-05-202-14/+42
* p9_sbe_tp_switch_gears -- skip i2c access outside of SBE platformJoe McGill2016-05-201-10/+3
* p9.core.common.initfile -- clear PSSCR[RL] for cache contained modeJoe McGill2016-05-201-1/+1
* Level 2 HWP for p9_sbe_attr_setup,p9_setup_sbe_configAnusha Reddy Rangareddygari2016-05-163-51/+115
* add core/cache initfilesJoe McGill2016-05-161-6/+66
* Level 2 HWP for p9_sbe_tp_chiplet_init3Soma BhanuTej2016-05-131-26/+49
* Move array of OP_TYPE strings from .H to .Ccrgeddes2016-05-131-1/+11
* Fix all incorrect copyright prologsStephen Cprek2016-05-131-1/+1
* p9_block_wakeup_intr Level 1Bilicon Patil2016-05-131-0/+107
* invoke cache SCOM initfilesJoe McGill2016-05-111-1/+40
* Enable p9_block_wakeup_intrSachin Gupta2016-05-091-0/+1
* p9_block_wakeup_intr Level 2Greg Still2016-05-091-13/+24
* Move array of OP_TYPE strings from .H to .Ccrgeddes2016-05-091-8/+1
* Fix all incorrect copyright prologsStephen Cprek2016-05-091-1/+0
* p9_block_wakeup_intr Level 1Bilicon Patil2016-05-091-0/+97
* HWP's for p9_perv_sbe_cmn,p9_sbe_arrayinit,p9_sbe_tp_arrayinitAnusha Reddy Rangareddygari2016-05-093-76/+156
* Level 2 HWP for p9_sbe_chiplet_resetAnusha Reddy Rangareddygari2016-05-091-6/+6
* Infrastructure updates to build cache initfile HWPs in import treeJoe McGill2016-05-062-0/+49
* change epsilon attribute definitions from arrays to scalarsJoe McGill2016-05-062-46/+96
* IPL optimized codesAnusha Reddy Rangareddygari2016-05-058-946/+558
* Level 2 HWP for p9_sbe_chiplet_pll_setupAnusha Reddy Rangareddygari2016-05-051-56/+141
* Changing error messages to save SBE spaceCHRISTINA L. GRAVES2016-05-051-33/+2
* add core/cache initfilesJoe McGill2016-05-046-0/+757
* Level 2 HWP for p9_sbe_nest_startclocksAnusha Reddy Rangareddygari2016-05-041-40/+40
* Level 2 HWP for p9_sbe_tp_chiplet_init3Anusha Reddy Rangareddygari2016-05-041-9/+10
* Single SEEPROM image for SBESachin Gupta2016-05-032-0/+2
* L2 - p9_build_smp HWPsThi Tran2016-05-021-10/+28
OpenPOWER on IntegriCloud