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* INT scan initfile change to add workaround for HW408972Jenny Huynh2017-09-121-0/+18
* p9_setup_bars -- support DD2 NPU SCOM address changesCHRISTINA L. GRAVES2017-09-121-0/+18
* Updating optimal larx/stcx dials for performanceLuke Murray2017-09-121-0/+24
* Added read ctr bad delay workaroundStephen Glancy2017-09-121-0/+17
* HW407123: Slow down xlink command rate for Nimbus DD1/2Jenny Huynh2017-09-121-0/+19
* Update filter pll settings as per HW407180Ben Gass2017-09-121-0/+18
* Fix for HW397129-set bit 52 in the ALTD_OPTION reg to keep MC fastpath enabledCHRISTINA L. GRAVES2017-09-121-0/+18
* Updating L3 LCO watermarks for HW406803Luke Murray2017-09-121-0/+17
* Adding good LCO settings to initfileLuke Murray2017-09-121-0/+41
* update DPLL and IVRM initsJoe McGill2017-09-121-0/+56
* p9_sbe_chiplet_reset,p9_sbe_arrayinitAnusha Reddy Rangareddygari2017-09-121-0/+33
* disable noise window for DD1 HW406577Shelton Leung2017-09-121-0/+17
* Attribute support of customization of Nimbus DD1 PCI reference clock speed.Thi Tran2017-09-121-2/+2
* HW406130: Reduce dma read requests from 16->8 in NX initsJenny Huynh2017-09-121-0/+18
* Add risklevel for HW399624 due to perf penalty; Add HW405851Nick Klazynski2017-09-121-0/+17
* p9_abist: Support for p9ndd2Markus Dobler2017-09-121-0/+17
* Add ec_abst ring to p9n.hw_imageThi Tran2017-09-121-0/+17
* HW405413 : NCU sends data out of orderAlex Taft2017-09-121-0/+17
* Scrubbing needs to stay off for DD2, bug HW405443Juan Medina2017-09-121-1/+2
* PM: GPE timer fix (HW389045 - Update Shadow copy of TSEL)Greg Still2017-09-121-0/+17
* Set NDL IOValids based on configured NV links.Ben Gass2017-09-121-0/+36
* p9_start_cbs updatesAnusha Reddy Rangareddygari2017-09-121-0/+18
* enable prefetch drop for better MC fairnessShelton Leung2017-09-121-1/+18
* Reducing rng pace rate from 2000 -> 300 for HW403701Jenny Huynh2017-09-121-0/+17
* Updates to run HW VREF cal by defaultStephen Glancy2017-09-121-0/+34
* adjust SRAM timingsJoe McGill2017-09-121-19/+2
* New dummy pulse pok bits (for L2/L3)Alex Taft2017-09-121-0/+34
* NPU scan/scom init updatesRyan Black2017-09-121-0/+17
* Add three WATs, remove IMC2, replace stop2 workaroundNick Klazynski2017-09-121-1/+52
* Add workaround for DDRPHY ODT config register erratum (ODT2, ODT3 bits swapped)Louis Stermole2017-09-121-0/+20
* Workaround to fix issue where Powerbus loses track of EQs in DD1Raja Das2017-09-121-0/+16
* reverting FIRs to master values, setting only bit 8Juan Medina2017-09-121-0/+19
* adding insert for soft fail threshold for dd1 and dd2Joshua Hannan2017-09-121-0/+17
* WAs for HW401811 HW402145 HW403465; DIS_MULTIPLE_TBLW on all modesNick Klazynski2017-09-121-2/+53
* amo cache disabled for dd1 for HW401780Shelton Leung2017-09-121-0/+17
* Adding HW363780 to NPU scom initfilesJenny Huynh2017-09-121-0/+18
* workarounds for HW399919 HW400898 HW398269 HW398269 HW399765Nick Klazynski2017-09-121-0/+137
* Added periodic cal fix - fixes bad delaysStephen Glancy2017-09-121-0/+18
* workaround for hw400932 atag corruptin in prespShelton Leung2017-09-121-0/+17
* dd1 workaround for hw400075 coherency errorShelton Leung2017-09-121-0/+17
* VITAL cleaning for DD2Anusha Reddy Rangareddygari2017-09-121-19/+1
* p9.core.scan.initfile -- mask local error from CC in EC perv LFIRJoe McGill2017-09-121-0/+17
* p9_sbe_tp_chiplet_init3 -- disable TP TOD hang pulseJoe McGill2017-09-121-0/+17
* Updating P9 L2 scan initfile to use attributesLuke Murray2017-09-121-0/+34
* FBC updates for HW383616, HW384245Joe McGill2017-09-121-0/+36
* Adding skip group dials for cache when chip=groupLuke Murray2017-09-121-0/+41
* Adding chip_ec_feature attributes for dd2 buildBen Gass2017-09-121-0/+1312
* add SS PLL settings to support 94 MHz PCI operationJoe McGill2017-09-121-0/+18
* p9_getecid -- set PCIE DD1.0x workaround attributesJoe McGill2017-09-121-0/+34
* Add MSS customization support from CRP0 Lx MVPDJoe McGill2017-09-121-35/+1
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