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* Revert "lpc_init: Correct LPC host controller timeout value"Jennifer A. Stofer2018-08-291-1/+1
| | | | | | | | | | | | | This reverts commit 77b6c7e6b123b32e37d07db91b0478a938a4d4a7. Change-Id: I95ffbf3404932c027093ea614ff979178292edeb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65113 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65129 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* lpc_init: Correct LPC host controller timeout valueJoachim Fenkes2018-08-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The LPC host controller has an interesting way to decode the timeout value. The left 4 bits are used for the "short wait" timeout, while the entire 8 bits are used for the "long wait" timeout. If the "short wait" timeout is 0xF, it is taken to be infinite, causing the host controller to hang if the slave doesn't respond. Change the timeout value from 0xFE to 0xEF, the correct maximum value that is not decoded to be infinity. Change-Id: Iaf1a5119a87338c24b1e324d814ade0b30353360 CQ: SW442999 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64850 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64856 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Tested-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable Core compatability Mode; Add HW443669Nick Klazynski2018-08-291-0/+41
| | | | | | | | | | | | | | | | | Change-Id: I7298d0ac0d7b9eb37213b9ad0b5571c480deaee2 CQ: HW443669 CQ: SW442796 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64432 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64440 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Use core target for HRMOR/URMOR scoms in p9_sbe_load_bootloaderDean Sanner2018-08-291-2/+2
| | | | | | | | | | | | | | | -Code was using EX target, which only results in core 0 working Change-Id: I2106a836f9ab73b32a37665758fbc6f8ab3a888c Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64403 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64404 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* nest updates for p9c DD1.3 native and p9c DD1.2 compatibility modesJoe McGill2018-08-293-14/+36
| | | | | | | | | | | | | | | | | | | | | | | HW 446279 - disable update for compat and native modes HW 439321 - disable update for compat, enable for native mode HW 443004 - disable update for compat and native modes HW 446453 - disable update for compat, enable for native mode Change-Id: I3dd1ed6075ff473adbaf342671dd977c53fb2f06 CQ: HW446279 CQ: HW439321 CQ: HW443004 CQ: HW446453 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64067 Reviewed-by: LUKE MURRAY <murrayl@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64082 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updates to permit synchronized SS PLL spreading via TODJoe McGill2018-08-294-14/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create EC feature attribute and user override attribute to control application of synchronized spreading. Default to enable synchronized spreading on Axone only. p9_sbe_npll_setup Conditionally skip existing unsynchronized spread enablement p9_tod_init Conditionally invoke spread sync routine after TOD network is running p9_ss_pll_sync Remove from repository, shift code into p9_tod_init to prevent need for mirroring into downstream repositories for FW consumption Change-Id: Ic32c800d58c260136b45fe9561989987d0a97ceb Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63494 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63503 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* SMF: SBE updates for SMF (URMOR set and CPMMR[Runtime Wakeup Mode] clear)Greg Still2018-08-294-28/+93
| | | | | | | | | | | | | | | | | | - set URMOR if MSR[S] bit is set in p9_sbe_load_bootloader - clear CPMMR[Runtime Wakeup Mode] in all cores in p9_sbe_select_ex to ensure Hostboot starts from known state Change-Id: I572a1d9e0ebf8e194c811e2b8c176d145b7361e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61812 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61817 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add hook to setup ATTR_SMF_CONFIGDean Sanner2018-08-281-0/+7
| | | | | | | | | | Read from scratch register and set SBE ATTR Change-Id: I5c9b7022fda7803ece8d438efafc5ae3787aafcc Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64412 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add prototype for releasing platform data pointer storage functionRichard J. Knight2018-08-282-4/+14
| | | | | | | | | | | | | | Change-Id: I94dbc2125a2c8e0a75f35df067f14c4ca01463d0 CQ:SW401034 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/45718 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/45726
* Introducing lpc utils source filespashabk-in2018-08-282-0/+26
| | | | | | | | | | | | | | | | | Including the dummy file so that the platforms could mirror this file without breaking existing implementation. Will follow up with separation of lpc_rw into source file on top of mirrored commits Change-Id: I4596af3a8740cb9593f135a0138e84299a5946ac Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64298 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joachim Fenkes <fenkes@de.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65269 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
* Move all text section to PIBMEM for axonespashabk-in2018-08-281-1/+2
| | | | | | | | | Change-Id: I5d1c008c86c154670414b868281152e1e19456e8 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62617 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Bump up axone pibmem size to 224KBspashabk-in2018-08-284-2/+234
| | | | | | | | | | Change-Id: I509164182308ff218ffd46b6ef10d62645cac071 RTC: 187456 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62211 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Axone image suffixspashabk-in2018-08-282-9/+9
| | | | | | | | | Change-Id: I9978bc6c7a6fd232aad3fa055929e3875082465e Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/65135 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* HCODE Make divide using DERP/DORP atomicDouglas Gilbert2018-08-231-1/+7
| | | | | | | | | | | | | | Change-Id: Ib7e1c88f7ac934ba551082f27231fff1bb3961dc CQ: SW443103 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64570 Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64578 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Project specific boot handlingspashabk-in2018-08-239-13/+98
| | | | | | | | | | | Macro based project config for pibmem repair RTC: 187456 Change-Id: Ibea93f343d1c63cdf6199cd89b8433b4f52bbf53 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/50762 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Add axone configspashabk-in2018-08-238-12/+464
| | | | | | | | | RTC: 187456 Change-Id: I6f82577cd457ae85dc6ae29edeb13cc1a8607543 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62089 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* [SBE-ARCH2] Format register dump and SBE Capturing the DataRaja Das2018-08-146-0/+347
| | | | | | | | | | | | | 1. Format of the register dump by SBE on the Host Memory (Interface) 2. SBE Capturing the architected state for all cores/threads and dumping it out in the hostboot reserved area. Change-Id: I80be7e3fa18679aa29aa2cda92eebbf85ce02fca Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59372 Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Avoid enabling smf bits in nmmu logic for P9Jenny Huynh2018-08-111-17/+0
| | | | | | | | | | | | | | | | | | No secure accelerators in P9, so avoid enabling nmmu smf bits that will otherwise cause sm table walk hangs. Nmmu will gate off addr15 when mm_cfg_xlat_ctl_urmor(0:2)=0b000. Change-Id: Ib008d6be5d32f45ebb2b66600e45828decf6fbf4 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64064 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Emmanuel Sacristan <esacris@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/64070 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* apply INT ARX clock gate disable to p9n DD2.0 hardwareJoe McGill2018-08-061-1/+1
| | | | | | | | | | | | | | | Change-Id: Id0d49c9146b990a8048a00abb7a2e4a6b2e9784a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63715 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63730 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Prevent Core-L2 Quiesce from removing PM_EXIT upon SPWUYue Du2018-08-011-1/+11
| | | | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I34f08519d2c86fec2f0ee0feb96a62bd826e31fa CQ: SW440301 cmvc-prereq: 1063483 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/61438 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62502 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Special wakeup bit correctionspashabk-in2018-07-311-3/+2
| | | | | | | Change-Id: I25d192ea8cea8de133f85cc0435503503a062028 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63606 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Validate OBUS DL lane failed indications during initial link trainingJoe McGill2018-07-312-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | Under certain circumstances, the DL logic can consume a spare lane during training, reporting that the link trained successfully but without reporting a lane sparing event in the FIR This commit adds a change to check for failed lanes in this case, and: - raise the lane spared indication in the FIR if a single lane is spared (no HWP error returned, but attention can trigger MFG IPL failure) - mark the link as failed to train if more than a single lane is marked spared, to trigger reconfig loop Change-Id: Iecc69bb1cad172d9c0b16c9b987cc6896e46216b CQ: SW439577 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63383 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Reviewed-by: Megan P. Nguyen <pmegan@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63394 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Disable HW439321 workaround in dd1.3Adam Hale2018-07-311-0/+17
| | | | | | | | | | | | | | Change-Id: Iefeff37efedc89567c229c1780ce0054b8279b36 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63221 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: SHELTON LEUNG <sleung@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: DANIEL C. HOWE <dchowe@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63371 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Enable CDD1.3's 4 risklevels (step 1)Nick Klazynski2018-07-271-6/+64
| | | | | | | | | | | | | | | | | | | | | | | | Risklevel 0 - DD1.2 compat, non-HANA (variant1/2 secure) Risklevel 1 - DD1.2 compat, HANA (no security) Risklevel 2 - Unused Risklevel 3 - Unused Risklevel 4 - DD1.3 native, non-HANA (variant1/2 secure) Risklevel 5 - DD1.3 native, HANA (no security) Step 2 will involve disabling all fixes to make CDD1.3 RL0/RL1 identical to CDD1.2 RL0/RL1. Change-Id: Ic7f031c97f2616a0eec0a965c52dcaed3ec698e3 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62935 Dev-Ready: James N. Klazynski <jklazyns@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62984 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_lpc_init: Improve resetJoachim Fenkes2018-07-272-13/+17
| | | | | | | | | | | | | | | | | | | | | | | The sequence to switch the LPC HC clock onto the nest clock temporarily was incorrect as it used the TP CPLT_CTRL0 register inasted of N3, so it never really switched the clocks during reset. Also, for good measure, keep the clock switched to the nest clock while we're resetting the LPC bus. (Bonus change: Decrease the sim delay cycles waiting for a command to complete.) Change-Id: I5e77fa056204639a96aad9c1eec4b7bc76d8e54b CQ: SW439536 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63279 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63286 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Remove ATTR_PROC_CHIP_MEM_TO_USEDan Crowell2018-07-271-12/+0
| | | | | | | | | | | | | | Cleaning up deprecated code Change-Id: I83d38acc12588ec2c1954920cfb083b0d0190aee Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63043 Reviewed-by: Prachi Gupta <pragupta@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63159
* Add MEM_PORT targetAndre Marin2018-07-272-2/+5
| | | | | | | | | | | | | | | Change-Id: Iff9984db164099845c8a5bc7ce28f412337f5925 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62917 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Matt K. Light <mklight@us.ibm.com> Reviewed-by: Daniel M. Crowell <dcrowell@us.ibm.com> Reviewed-by: Louis Stermole <stermole@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63011 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Initf procedure updates for CumulusAnusha Reddy Rangareddygari2018-07-272-4/+121
| | | | | | | | | | | | | Change-Id: Ieba2a677f48c9632e41020b9a48be7375c6eb31a CQ: SW437518 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62384 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SRINIVAS V. POLISETTY <srinivan@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62400 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Support special wakeup for SRESETspashabk-in2018-07-263-7/+162
| | | | | | | | | | | Introduce new mode in stop instruction to assert special wakeup and deassert it Change-Id: Ie0648040b4c8b120468c4d03748a91f3ec78a06a Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63026 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: RAJA DAS <rajadas2@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Get capabilities spec syncspashabk-in2018-07-246-67/+134
| | | | | | | | | | | | | Sync with fifo spec - 1.5c PSU spec - 0.9e Change-Id: I16048b0a52c47da5b713cbbc28d25039114d9a30 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61251 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit a0a932369074e874a14685bda3548adf6dc8ac28) Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/59929
* Handling special wakeup assert/deassert mis-match in PM Reset/Init on MALFAmit Tendolkar2018-07-222-4/+16
| | | | | | | | | | | | | | | | | | | | - Skip deassert special wakeup in PM Init when in PM Malf path - Attribute changes to default HB to disable MALF and PM FFDC enablement on IPL - Attribute to track Malf Flow across PM Reset and Init - Do not fail PM reset in Malf Flow, if auto special wakeup could not be set Change-Id: I5c730c818bbf886b8db7fc497cfb62c7a6c9c7f0 CQ: SW437841 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62528 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62541 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updated gerrit hostnameSumit Kumar2018-07-201-2/+2
| | | | | | | Change-Id: Ie55fd178758591fbed96187c94c2cc1b00eac024 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62924 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9.pci.scan.initfile -- replace 62028 implementation with initfile entryJoe McGill2018-07-192-111/+0
| | | | | | | | | | | | | | | | | | | | | | 62028 added a workaround for SW 430383, using a manual re-scan of the ring hardcoded to flip the desired bits because engineering data was not yet available for the necessary spies This commit removes the SBE manual scan sequence and sets the necessary chicken switches by the newly added spy entries Change-Id: I912f190ab44c320f9bd142ce626570d34ec0b00f CQ: SW438480 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62675 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/62710 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Updating backing buildSachin Gupta2018-07-191-1/+1
| | | | | | | Change-Id: I862d52f40b5459d73c0dafe6c84611a3d8c7726f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62873 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* STOP: remove chiplet enable drop in core_poweron for multicast scomYue Du2018-07-181-4/+1
| | | | | | | | | | | | | | | | Key_Cronus_Test=PM_REGRESS Change-Id: I388c81cc1af356231daa4a11702a3a84dcc222c9 CQ: SW437797 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62302 Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Reviewed-by: RAHUL BATRA <rbatra@us.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62326 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabledJoe McGill2018-07-183-0/+30
| | | | | | | | | | | | | | | Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Avoid spurious Malf Alert (HMI) to PHYP in PM Complex Reset/SuspendAmit Tendolkar2018-07-131-0/+7
| | | | | | | | | | | | | | | | | | | Reseting the engines potentially causes another to send the PM Malf Alert to PHYP. Disable in PM Reset and let SGPE re-enable in PM Init. Added a similar safe check and disable in MPIPL path for pm_suspend Change-Id: If9fd572d156a8f280b0fd204175e5ccf0969b249 CQ: SW436905 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62135 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Prem Shanker Jha <premjha2@in.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62298 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Clockgate disable workaround for HW452921Nick Klazynski2018-07-131-3/+3
| | | | | | | | | | | | | | | Change-Id: I09ec35894a488f0c9e2b03d8726b3a5a3ce08fcf CQ: HW452921 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62048 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62067 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Cleanup: Updated Mvpd access function and removal of unused ringsClaus Michael Olsen2018-07-133-18/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Removed the function that converts the outdated RS4v2 header format to the current RS4v3 header format in the Mvpd accessor functions, mvpdRingFundFind(). This can be done since all Mvpd in existance on any of our supported P9 systems (i.e., >=P9N DD20) use RS4v3. - Removed two #R rings which are no longer supported since P9n DD10. Because these rings happen to be located at the end of the TOR instance ring sections, it will alter the image, but will not interfere with the traversing of the ringSection image due to the way chiplet and common/instance sub-sections are partitioned. Key_Cronus_Test=XIP_REGRESS Change-Id: I39740a099b224bfade8a97a057453b85498e5880 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61100 Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Michael C. Sgro <mcs793@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Cronus HW CI <cronushw-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61288 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Marking CME sram addr and cntrl register for whitelistPrasad Bg Ranganath2018-07-131-0/+4
| | | | | | | | | | | | Change-Id: I480a7bb511718cbd2e04a2ca5b41585ce9ce1606 CQ:SW437569 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61879 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: SANTOSH BALASUBRAMANIAN <sbalasub@in.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61881
* Secure memory allocation and setupJenny Huynh2018-07-129-16/+249
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | p9_mss_eff_grouping.C: - determines whether secure mem is requested, reserves smf space - always reserve smf at end of range because of end-of-range bit - set addr15 when reporting smf base address - mask off group_id(0) via chip address extension if smf is enabled - updated to set value of attr_smf_enabled - enhanced error reporting with smf config/supported values - made values reported to attr_mss_mcs_group_32 more clear p9_mss_setup_bars.C: - set MCFGPA/MCFGPMA registers with SMF data - fixed scom registers for MCFGPA/MCFGPMA hole setup - added note to leave MCFIR_invalid_smf masked for HW451708/HW451711 - added assert to check for HOLE1 and SMF enable overlaps p9_query_mssinfo.C: - updated to print out SMF reservations - print out HTM/OCC/SMF reservations regardless of mirroring enable p9_fbc_utils.C: - prevent group_id(0)=1 from affecting mappable memory ranges p9_sbe_fabricinit.C: - mask off group_id(0) via chip address extension if smf is enabled p9_setup_sbe_config.C, p9_sbe_attr_setup.C: - use scratch_reg6 bit(16) to pass smf_config value initfiles: - removed setup to use other addr bits as secure bit; core only uses addr15 - added setup for ncu addr15 value in hcode - always set addr15 config bit in bridge unit if smf is supported - set addr15 bit across all mcs if smf is enabled - added in settings to enable smf in nmmu unit - hardcode group_id(0) bit in chipext mask for bridge unit if smf is supported attributes: - ATTR_SMF_ENABLE is a system level attribute - changed SMF_ENABLE->SMF_CONFIG; smf_enabled will be (config && supported) CQ:HW451708 CQ:HW451711 Change-Id: I6cf85600354baa322e959c922f596ecc5c68a458 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57322 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Dev-Ready: Brent Wieman <bwieman@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/57347 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Inverted logic of hasClock bit in Clock Status registerRaja Das2018-07-121-0/+4
| | | | | | | | | | | | | CQ: SW437571 Change-Id: I9101adc63225a97aeddf445519fa660d961c3d9c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61463 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Brian T. Vanderpool <vanderp@us.ibm.com> Reviewed-by: RANGANATHPRASAD G. BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61471 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* Fix in quisceSachin Gupta2018-07-122-8/+6
| | | | | | | | | | | | Change-Id: Id64bf0b948e65b142e47b777f937ffe4bf530d55 CQ: SW437514 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62208 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Shakeeb A. Pasha B K <shakeebbk@in.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit c2da12c625e492988947fdb872424f10d0b8b4b1) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62293
* Suspend async task on quiesce SBEspashabk-in2018-07-121-19/+30
| | | | | | | | | | Change-Id: Icfe25bdd137c1f30a8a1c210fa6d935612d61e68 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61358 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit 98d57c57fdd8ca52b4f7a71345ba5d4322a3aff9) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62204
* Skip select master EX on slave SBEspashabk-in2018-07-121-7/+10
| | | | | | | | | | | CQ: SW432854 Change-Id: I5bd4f32e77fe8abb7193f5bcff6f298c75b65b8c Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62015 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com> (cherry picked from commit ccafed91129314fb72a13321c4826f64685f2fa7) Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62117
* p9_sbe_check_quiesce -- restore call to p9_int_scrub_cachesJoe McGill2018-07-123-3/+53
| | | | | | | | | | | | | | | | | | | | | | 52512 removed code related to the DD1 SW based INT reset sequence, to leave only the HW based reset in production code for DD2 and beyond. It also erroneously removed the call to/code for p9_int_scrub_caches. This commit restores the subroutine, and invokes it prior to the HW quiesce/sync reset into order to scrub/flush the EQC, VPC, IVC, and SBC caches. Change-Id: I051117e3a18c55aea7267e53eea1652f0cff9790 CQ: SW431898 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62227 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62243 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* set PEC disable store thread based ordering chicken switchesJoe McGill2018-07-103-1/+141
| | | | | | | | | | | | | | | | Change-Id: I2d9aed7833a1bf43c797689d50ff32794ef54cff CQ: SW430383 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62028 Reviewed-by: Kevin F. Reick <reick@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: Dean Sanner <dsanner@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62042 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* allow option to enforce mirroring of all system memoryJoe McGill2018-07-071-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nest_attributes.xml: add REQUESTED enum to ATTR_MRW_HW_MIRRORING_ENABLE, takes prior behavior of TRUE enum new TRUE enum behavior enforces that all memory will be mirrored p9_mss_eff_grouping: prohibit group formation of size 1, 2 (cross-MCS), or 3 if ATTR_MRW_HW_MIRRORING_ENABLE is TRUE -- this will ensure that all groups formed support mirroring commit log for each DIMM which is ungrouped p9_mss_setup_bars, p9_query_mssinfo, p9_setup_bars: Minor changes to adapt to new enum definition Change-Id: I328b7b063bf79d534b1b466560309c0ccae5a4f5 CQ: SW436871 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61483 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Nicholas E. Bofferding <bofferdn@us.ibm.com> Reviewed-by: Ravi Medikonduru <ravimed1@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61496 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* p9_sbe_tp_chiplet_init3: Set up oscillator error mask based on MF osc settingJoachim Fenkes2018-07-042-29/+32
| | | | | | | | | | | | | | | | | | | | | | | | On Cumulus, set up the oscerr mask (0102001A) such that errors on unused MF/PCI oscillators are masked (based on the setup in RC3), making sure the corresponding FIR bit (TP LFIR bit 37) will not report false positives. Keep the mask constant for Nimbus as only MF oscillator 0 is in use there. This reverts most of commit ce194c5cd773bdabd093b3aa44c2b3d3bcfb58e5 because a correct mask setting here obviates the need for selective FIR masking. Change-Id: Ib49704fb50fc1e62168cc4cd06841d068c488914 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61365 Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Reviewed-by: Joseph J. McGill <jmcgill@us.ibm.com> Reviewed-by: Zane C. Shelley <zshelle@us.ibm.com> Reviewed-by: Thi N. Tran <thi@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/61370 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
* PM: Added support for enable disable of 24x7 IMA.Prem Shanker Jha2018-07-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | Commit incorporates an ability to enable or disable 24x7 IMA. It reads an attribute and populates a field of QPMR header. 24x7 firmware is expected to read this field and enable or disable 24x7 IMA by itself. Key_Cronus_Test=NO_TEST Change-Id: I1f1fc738a58f11346f7972eb3c547aac0e2f805f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59443 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com> Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com> Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com> Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com> Reviewed-by: RANGANATHPRASAD BRAHMASAMUDRA <prasadbgr@in.ibm.com> Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com> Reviewed-by: Gregory S. Still <stillgs@us.ibm.com> Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/59450 Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
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