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| author | Joe McGill <jmcgill@us.ibm.com> | 2018-07-09 16:10:39 -0500 |
|---|---|---|
| committer | Sachin Gupta <sgupta2m@in.ibm.com> | 2018-07-18 00:38:58 -0400 |
| commit | c8fede9e612b57f52e301ee13bbec980ebf01808 (patch) | |
| tree | 7c8f4979d334fe391cc0708245da9223856fbea1 | |
| parent | d5794d13060d1ae0f51b9bf3d51dc479110cc7e6 (diff) | |
| download | talos-sbe-c8fede9e612b57f52e301ee13bbec980ebf01808.tar.gz talos-sbe-c8fede9e612b57f52e301ee13bbec980ebf01808.zip | |
p9_sbe_scominit -- set XSCOM BAR in secure memory with SMF enabled
Change-Id: I7e3b39bb75ad8ee3983f4b4352d08369fe6bfc5c
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62065
Tested-by: Jenkins Server <pfd-jenkins+hostboot@us.ibm.com>
Tested-by: HWSV CI <hwsv-ci+hostboot@us.ibm.com>
Tested-by: PPE CI <ppe-ci+hostboot@us.ibm.com>
Tested-by: Hostboot CI <hostboot-ci+hostboot@us.ibm.com>
Reviewed-by: Dean Sanner <dsanner@us.ibm.com>
Reviewed-by: Thi N. Tran <thi@us.ibm.com>
Reviewed-by: Jenny Huynh <jhuynh@us.ibm.com>
Reviewed-by: Jennifer A. Stofer <stofer@us.ibm.com>
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/62074
Reviewed-by: Sachin Gupta <sgupta2m@in.ibm.com>
3 files changed, 30 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 97d2c811..79926591 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/src/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -79,6 +79,9 @@ const uint8_t CHIP_ADDRESS_EXTENSION_GROUP_ID_MASK_SMF_ENABLE = 0x8; const uint64_t MAX_INTERLEAVE_GROUP_SIZE = 0x40000000000ULL; // 4_TB const uint64_t MAX_INTERLEAVE_GROUP_SIZE_HW423589_OPTION2 = 0x8000000000ULL; // 512_GB +// XSCOM BAR offset, with SMF enabled +const uint64_t XSCOM_BAR_SMF_OFFSET = 0x0001000000000000ULL; + //------------------------------------------------------------------------------ // Function prototypes //------------------------------------------------------------------------------ diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C index 18ce7098..626063cc 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_load_bootloader.C @@ -401,6 +401,8 @@ get_bootloader_config_data( fapi2::buffer<uint64_t> l_cbs_cs; BootloaderConfigData_t l_bootloader_config_data; + fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED_Type l_smf_supported; + fapi2::ATTR_SMF_CONFIG_Type l_smf_config; FAPI_DBG("Start"); @@ -420,8 +422,22 @@ get_bootloader_config_data( FAPI_SYSTEM, l_bootloader_config_data.xscomBAR), "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED, + i_master_chip_target, + l_smf_supported), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, + FAPI_SYSTEM, + l_smf_config), + "Error from FAPI_ATTR_GET (ATTR_SMF_CONFIG)"); + l_bootloader_config_data.xscomBAR += l_chip_base_address_mmio; + if (l_smf_config && l_smf_supported) + { + l_bootloader_config_data.xscomBAR += XSCOM_BAR_SMF_OFFSET; + } + // LPC BAR offset FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, diff --git a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C index 1f6fc5d3..431ba12a 100644 --- a/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C +++ b/src/import/chips/p9/procedures/hwp/nest/p9_sbe_scominit.C @@ -178,14 +178,25 @@ p9_sbe_scominit(const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) { fapi2::buffer<uint64_t> l_xscom_bar; uint64_t l_xscom_bar_offset; + fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED_Type l_smf_supported; + fapi2::ATTR_SMF_CONFIG_Type l_smf_config; FAPI_DBG("Configuring XSCOM BAR"); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET, FAPI_SYSTEM, l_xscom_bar_offset), "Error from FAPI_ATTR_GET (ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED, i_target, l_smf_supported), + "Error from FAPI_ATTR_GET (ATTR_CHIP_EC_FEATURE_SMF_SUPPORTED)"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SMF_CONFIG, fapi2::Target<fapi2::TARGET_TYPE_SYSTEM>(), l_smf_config), + "Error from FAPI_ATTR_GET (ATTR_SMF_CONFIG)"); l_xscom_bar = l_base_addr_mmio; l_xscom_bar += l_xscom_bar_offset; + if (l_smf_config && l_smf_supported) + { + l_xscom_bar += XSCOM_BAR_SMF_OFFSET; + } + FAPI_ASSERT((l_xscom_bar & XSCOM_BAR_MASK) == 0, fapi2::P9_SBE_SCOMINIT_XSCOM_BAR_ATTR_ERR() .set_TARGET(i_target) |
