diff options
Diffstat (limited to 'src/test/framework/etc/patches/chip.act.patch')
| -rw-r--r-- | src/test/framework/etc/patches/chip.act.patch | 146 |
1 files changed, 0 insertions, 146 deletions
diff --git a/src/test/framework/etc/patches/chip.act.patch b/src/test/framework/etc/patches/chip.act.patch deleted file mode 100644 index 0b9cf0f0..00000000 --- a/src/test/framework/etc/patches/chip.act.patch +++ /dev/null @@ -1,146 +0,0 @@ -184,240c184 -< # ========================================================================== -< # Actions for p9_adu_access and p9_adu_setup procedures -< # ========================================================================== -< #If a read/write is done to the ALTD_DATA Register set the ALTD_STATUS Register so things are as expected -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS Register] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< -< #Set the ALTD_STATUS Register so these bits are set: -< #FBC_ALTD_BUSY = WAIT_CMD_ARBIT = WAIT_RESP = OVERRUN_ERR = AUTOINC_ERR = COMMAND_ERR = ADDRESS_ERR = COMMAND_HANG_ERR = DATA_HANG_ERR = PBINIT_MISSING = ECC_CE = ECC_UE = ECC_SUE = 0 -< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,AND] DATA=[LITERAL(64,001FDFFF FFFF1FFF)] -< EFFECT: TARGET=[REG(0x00090003)] OP=[BUF,OR] DATA=[LITERAL(64,30000000 00000000)] -< } -< -< #If a read/write is done to the ALTD_DATA Register and the Address only bit is not set then set the DATA_DONE bit to 1 -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS[DATA_DONE] bit] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] -< -< #Set the DATA_DONE bit -< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] -< } -< -< #If a read/write is done to the ALTD_DATA Register and the Data only bit is not set then set the ADDR_DONE bit to 1 -< CAUSE_EFFECT{ -< LABEL=[ADU Read or write to set ALTD_STATUS[ADDR_DONE] bit] -< #If the data register is read -< WATCH_READ=[REG(0x00090004)] -< #If the data register is written -< WATCH=[REG(0x00090004)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] -< -< #Set the ADDR_DONE bit -< EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] -< } -< -< #If a read is done to the ALTD_CMD Register and it sets the lock set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set -< CAUSE_EFFECT{ -< LABEL=[ADU Write to set ALTD_STATUS_BUSY] -< WATCH=[REG(0x00090001)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[11] -< -< #Set the ALTD_STATUS Register so the ALTD_STATUS_BUSY bit is set -< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,ON] BIT=[0] -< } -< #If a write is done to the ALD_CMD_REG to set the FBC_ALTD_START_OP bit it should turn FBC_ALTD_BUSY off -< CAUSE_EFFECT{ -< LABEL=[ADU Write to ALTD_CMD_REG to unset set ALTD_STATUS FBC_ALTD_BUSY bit] -< WATCH=[REG(0x00090001)] -< CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] ---- -> ### ADU ACTIONS - READ WRITE RESET ### -242,243c186,265 -< #Unset the ALTD_STATUS Register so the ALTD_STATUS_BUSY is unset -< EFFECT: TARGET=[REG(0x090003)] OP=[BIT,OFF] BIT=[0] ---- -> # Reset ALTD Status Reg -> CAUSE_EFFECT { -> LABEL=[RESET FSM ALTD Status Register] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[4] #Reset FSM bit -> EFFECT: TARGET=[REG(0x00090003)] OP=[EQUALTO,BUF] DATA=[LITERAL(64,00000000 00000000)] -> } -> -> # ADU Transaction Complete Status - Busy Bit Low -> CAUSE_EFFECT { -> LABEL=[ALTD_BUSY Status Register Clear] -> WATCH=[REG(0x00090003)] # ALTD_Status_Reg -> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> CAUSE: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AUTO INCR Mode OFF -> -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,OFF] BIT=[0] #BUSY Bit low -> } -> -> # Read without AutoIncr -> CAUSE_EFFECT{ -> LABEL=[READ Mainstore without AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> -> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Read with AutoIncr -> CAUSE_EFFECT{ -> LABEL=[READ Mainstore with AutoIncr] -> WATCH_READ=[REG(0x00090004)] # ALTD_Data_reg -> -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[5] #READ ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on -> -> EFFECT: TARGET=[MODULE(readMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # read the memory -> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64,00000000 0000FFFF)] # incr addr reg by 8 -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Write without AutoIncr -> CAUSE_EFFECT{ -> LABEL=[WRITE Mainstore without AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_Reg -> WATCH=[REG(0x00090004)] # ALTD_Data_reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[19] #AutoInc bit off -> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -> } -> -> # Write with AutoIncr -> CAUSE_EFFECT{ -> LABEL=[WRITE Mainstore with AutoIncr] -> WATCH=[REG(0x00090001)] # ALTD_Cmd_reg -> WATCH=[REG(0x00090004)] # ALTD_Data_reg -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[2] #start ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[5] #WRITE ADU Operation -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[6] #addr Only Type Command -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,OFF] BIT=[7] #data -> CAUSE: TARGET=[REG(0x00090001)] OP=[BIT,ON] BIT=[19] #AutoInc bit on -> EFFECT: TARGET=[MODULE(writeMainstore, 0x00090000)] OP=[MODULECALL] DATA=[REG(0x00090004)] # write the memory -> EFFECT: TARGET=[REG(0x00090000)] OP=[INCREMENT,MASK] INCVAL=[8] MASK=[LITERAL(64, 00000000 0000FFFF)] # incr addr reg by 8 -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[2] #FBC_ALTD_ADDR_DONE -> EFFECT: TARGET=[REG(0x00090003)] OP=[BIT,ON] BIT=[3] #FBC_ALTD_DATA_DONE -265a288 -> EFFECT: TARGET=[MODULE(executeInstruction, MYCORE)] OP=[MODULECALL] DATA=[REG(MYCHIPLET, 0x00010A4F)] |
