diff options
Diffstat (limited to 'src/import')
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C | 16 |
1 files changed, 9 insertions, 7 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C index 9fe395df..f7997e9e 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -184,6 +184,15 @@ fapi2::ReturnCode p9_sbe_select_ex( auto l_eq_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_EQ> (fapi2::TARGET_STATE_FUNCTIONAL ); + // Prior to writing to PM registers, ensure that the PPM write disable + // bit on the Core Power Management Mode Register is cleared for all cores + for (auto& core : l_core_functional_vector) + { + FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", core.getChipletNumber()); + l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>(); + FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64)); + } + // Read the "FORCE_ALL" attribute fapi2::ATTR_SYS_FORCE_ALL_CORES_Type l_attr_force_all; FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, @@ -378,13 +387,6 @@ fapi2::ReturnCode p9_sbe_select_ex( FAPI_DBG("Scoreboard values for OCC: Core 0x%016llX EX 0x%016llX", l_core_config, l_quad_config); - // Prior to writing to PFET_DELAY register, ensure that the PPM write disable - // bit on the Core Power Management Mode Register is cleared - FAPI_DBG("Clearing WRITE_DISABLE bit in core %d", l_core_num); - l_data64.flush<0>().setBit<C_CPPM_CPMMR_PPM_WRITE_DISABLE>(); - - FAPI_TRY(fapi2::putScom(core, C_CPPM_CPMMR_CLEAR , l_data64)); - // Write the default PFET Controller Delay values for the Core // as it will be used for istep 4 FAPI_DBG("Setting PFET Delays in core %d", l_core_num); |
