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-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C78
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H17
-rw-r--r--src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C16
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C21
-rw-r--r--src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml24
5 files changed, 86 insertions, 70 deletions
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C
index ce9c2084..1c1481a3 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.C
@@ -72,7 +72,7 @@ typedef enum
fapi2::ReturnCode
p9_collect_deadman_ffdc (
const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_core,
- const p9SbeCheckMasterStop15RC_t i_reason )
+ const uint32_t i_reason )
{
FAPI_IMP (">> p9_collect_deadman_ffdc RC: 0x%.8X", i_reason);
fapi2::ReturnCode l_rc;
@@ -127,9 +127,11 @@ p9_collect_deadman_ffdc (
if (l_rc == fapi2::FAPI2_RC_SUCCESS)
{
// Copy bits 0-31 of SCOM data to the FFDC buffer entry at bits:
- (l_addrIdx % 2) ? // even iteration?
- (l_data64.extract<0, 32, 0> (l_dmanFfdcScoms[l_buffIdx])) : // 0-31
- (l_data64.extract<0, 32, 32>(l_dmanFfdcScoms[l_buffIdx])); // 32-63
+ (l_addrIdx & 0x01) ?
+ // Odd Index: Copy data bits 0-31 to bits 32-63 of buffer
+ (l_data64.extract<0, 32, 32> (l_dmanFfdcScoms[l_buffIdx])) :
+ // Even Indiex: Copy data bits 0-31 to bits 0-31 of buffer
+ (l_data64.extract<0, 32, 0> (l_dmanFfdcScoms[l_buffIdx])); // 0-31
}
else // data already defaulted, optimize after debug
{
@@ -206,30 +208,66 @@ p9_collect_deadman_ffdc (
l_rc = fapi2::getScom ( l_eq, EQ_ATOMIC_LOCK_REG,
l_dmanFfdcScoms[FFDC_____EQ_ATOMIC_LOCK_REG] );
- // Read & add Core SCOM to the FFDC buffer
- l_rc = fapi2::getScom ( i_core,
- C_PPM_SSHSRC,
- l_data64 );
+ // Read & add Core SCOM(s) to the FFDC buffer
+ const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM;
+ fapi2::ATTR_FUSED_CORE_MODE_Type l_attr_fused_mode;
+ FAPI_ATTR_GET ( fapi2::ATTR_FUSED_CORE_MODE,
+ FAPI_SYSTEM,
+ l_attr_fused_mode );
- if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+ for ( auto& l_core : l_ex.getChildren <fapi2::TARGET_TYPE_CORE>
+ (fapi2::TARGET_STATE_FUNCTIONAL) )
{
- // C0: pack bits 0-31 of SCOM data to bits 0-31 of buffer entry
- l_data64.extract<0, 32, 0> (
- l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32]);
- }
+ bool l_read = false;
- // else just use the default
+ if (l_core == i_core)
+ {
+ // always read the core that was saved away
+ l_read = true;
+ }
+ else
+ {
+ // read sibling core data only if in fused mode
+ if (l_attr_fused_mode == fapi2::ENUM_ATTR_FUSED_CORE_MODE_CORE_FUSED)
+ {
+ l_read = true;
+ }
+ }
- // @TODO via RTC: 173949
- // Collect the sibling core register C_PPM_SSHSRC once we have the
- // ATTR_FUSED_CORE_MODE function
+ if (l_read == true)
+ {
+ l_rc = fapi2::getScom ( l_core,
+ C_PPM_SSHSRC,
+ l_data64 );
+
+ if (l_rc == fapi2::FAPI2_RC_SUCCESS)
+ {
+ uint8_t l_chipUnitPos = 0;
+ FAPI_ATTR_GET ( fapi2::ATTR_CHIP_UNIT_POS,
+ l_core,
+ l_chipUnitPos );
+
+ (l_chipUnitPos & 0x01) ?
+ // Odd: pack bits 0-31 of SCOM data to bits 32-63 of buffer entry
+ (l_data64.extract<0, 32, 32> (
+ l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32] )) :
+ // Even: pack bits 0-31 of SCOM data to bits 0-31 of buffer entry
+ (l_data64.extract<0, 32, 0> (
+ l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32] ));
+ }
+
+ // else just use the default
+ }
+
+ // else just use the default
+ }
// Add FFDC to a single FAPI RC, to avoid code bloat from multiple
// generated ffdc classes & error info classes per FAPI RC.
// Note, we are adding 16 FFDC members. Limit is 20.
FAPI_ASSERT ( false,
- fapi2::CHECK_MASTER_STOP15_FAILED ()
- .set_SBE_CHK_MASTER_STOP15_RC (i_reason)
+ fapi2::CHECK_MASTER_STOP15_DEADMAN_TIMEOUT ()
+ .set_DEADMAN_TIMEOUT_REASON (i_reason)
.set_CORE_TARGET (i_core)
.set_PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR (
l_dmanFfdcScoms[FFDC_____PU_OCB_OCI_OCCFLG32__CCSR32])
@@ -241,6 +279,8 @@ p9_collect_deadman_ffdc (
l_dmanFfdcScoms[FFDC_____EX_CME_SICR_64])
.set_EX_CME_LCL_SISR_SCOM (
l_dmanFfdcScoms[FFDC_____EX_CME_SISR_64])
+ .set_EQ_ATOMIC_LOCK_REG (
+ l_dmanFfdcScoms[FFDC_____EQ_ATOMIC_LOCK_REG])
.set_C0_PPM_SSHSRC__C1_PPM_SSHSRC (
l_dmanFfdcScoms[FFDC_____EC0_PPM_SSHSRC32__EC1_PPM_SSHSRC32])
.set_SGPE_XSR__IAR (l_v_reg_ffdc_sgpe[REG_FFDC_IDX_XSR_IAR])
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H
index f6257d68..b5046bfd 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_collect_deadman_ffdc.H
@@ -30,7 +30,7 @@
/// *HWP HW Backup Owner : Brian Vanderpool <vanderp@us.ibm.com>
/// *HWP FW Owner : Amit Tendolkar <amit.tendolkar@in.ibm.com>
/// *HWP Team : PM
-/// *HWP Level : 2
+/// *HWP Level : 3
/// *HWP Consumed by : SBE
#ifndef __P9_COLLECT_DEADMAN_FFDC_H__
#define __P9_COLLECT_DEADMAN_FFDC_H__
@@ -41,25 +41,18 @@
#include <return_code.H>
#include <hwp_return_codes.H>
-typedef enum
-{
- CHECK_MASTER_STOP15_INVALID_STATE,
- CHECK_MASTER_STOP15_TIMEDOUT,
- CHECK_MASTER_STOP15_UNKNOWN
-} p9SbeCheckMasterStop15RC_t;
-
-/// @typedef p9_ppe_state_FP_t
+/// @typedef p9_collect_deadman_ffdc_FP_t
/// function pointer typedef definition for HWP call support
typedef fapi2::ReturnCode (*p9_collect_deadman_ffdc_FP_t) (
const fapi2::Target<fapi2::TARGET_TYPE_CORE>&,
- const p9SbeCheckMasterStop15RC_t
+ const uint32_t
);
//------------------------------------------------------------------------------
// Function prototypes
//------------------------------------------------------------------------------
-/// @brief Collects FFDC related to the deadman failure
+/// @brief Collects FFDC related to the deadman timeout failure
/// @param [in] i_target Master core target which failed entering STOP15
/// @param [in] i_reason Reason code to be added to the FFDC data
/// @return On success, a ReturnCode object with the input HWP return code
@@ -69,6 +62,6 @@ typedef fapi2::ReturnCode (*p9_collect_deadman_ffdc_FP_t) (
fapi2::ReturnCode
p9_collect_deadman_ffdc (
const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target,
- const p9SbeCheckMasterStop15RC_t i_reason );
+ const uint32_t i_reason );
#endif // __P9_COLLECT_DEADMAN_FFDC_H__
diff --git a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C
index a7d11700..517e78f7 100644
--- a/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C
+++ b/src/import/chips/p9/procedures/hwp/lib/p9_sbe_ppe_ffdc.C
@@ -170,19 +170,21 @@ p9_sbe_ppe_ffdc (
if (l_rc == fapi2::FAPI2_RC_SUCCESS)
{
- if (i % 2)
+ if (i & 0x01)
{
- // pack into bits 0-31 of ithe ffdc vector element
+ // Odd Index
+ // pack into bits 32-63 of the ffdc vector element
o_v_ppe_reg_ffdc[l_sprFfdcIdx] =
- (o_v_ppe_reg_ffdc[l_sprFfdcIdx] & 0x00000000FFFFFFFFULL) |
- ((uint64_t) l_data32() << 32);
+ (o_v_ppe_reg_ffdc[l_sprFfdcIdx] & 0xFFFFFFFF00000000ULL) |
+ (l_data32());
}
else
{
- // pack into bits 32-63 of the ffdc vector element
+ // Even Index
+ // pack into bits 0-31 of ithe ffdc vector element
o_v_ppe_reg_ffdc[l_sprFfdcIdx] =
- (o_v_ppe_reg_ffdc[l_sprFfdcIdx] & 0xFFFFFFFF00000000ULL) |
- (l_data32());
+ (o_v_ppe_reg_ffdc[l_sprFfdcIdx] & 0x00000000FFFFFFFFULL) |
+ ((uint64_t) l_data32() << 32);
}
}
else
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C
index 09455513..22780175 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_check_master_stop15.C
@@ -58,10 +58,6 @@
#include <p9_pm_stop_history.H>
#include <p9_quad_scom_addresses.H>
-#ifdef DD2
- #include <p9_collect_deadman_ffdc.H>
-#endif
-
// -----------------------------------------------------------------------------
// Function definitions
// -----------------------------------------------------------------------------
@@ -131,17 +127,12 @@ fapi2::ReturnCode p9_sbe_check_master_stop15(
}
else
{
-#ifdef DD2
- FAPI_TRY ( p9_collect_deadman_ffdc (
- i_target,
- CHECK_MASTER_STOP15_INVALID_STATE ));
-#else
- // DD1 has a memory crunch on SBE
- FAPI_ASSERT ( false,
- fapi2::CHECK_MASTER_STOP15_INVALID_STATE()
- .set_STOP_HISTORY(l_data64),
- "STOP 15 error" );
-#endif
+ /*
+ * This is a fail code,however, FFDC should be collected via a separate
+ * call to p9_collect_deadman_ffdc. Avoiding FAPI_ASSERT() as an
+ * optimization
+ */
+ return fapi2::RC_CHECK_MASTER_STOP15_INVALID_STATE;
}
// @todo RTC 162331 These should work but don't..... follow-up later
diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml
index bc35618b..54043657 100644
--- a/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml
+++ b/src/import/chips/p9/procedures/xml/error_info/p9_sbe_check_master_stop15_errors.xml
@@ -44,29 +44,15 @@
Indicates the targeted core is no longer pending entering a STOP state
but the achieved level is not appropriate.
</description>
- <ffdc>CORE_TARGET</ffdc>
- <ffdc>STOP_HISTORY</ffdc>
- <callout>
- <procedure>CODE</procedure>
- <priority>HIGH</priority>
- </callout>
- <callout>
- <procedure>LVL_SUPPORT</procedure>
- <priority>LOW</priority>
- </callout>
- <deconfigure>
- <target>CORE_TARGET</target>
- </deconfigure>
</hwpError>
<!-- ******************************************************************** -->
<hwpError>
<sbeError/>
- <rc>RC_CHECK_MASTER_STOP15_FAILED</rc>
+ <rc>RC_CHECK_MASTER_STOP15_DEADMAN_TIMEOUT</rc>
<description>
- Indicates the targeted core(s) are no longer pending entering a STOP state
- but the achieved level is not appropriate, or the deadman loop timed out.
+ SBE deadman timer fired with reason set in DEADMAN_TIMEOUT_REASON
</description>
- <ffdc>SBE_CHK_MASTER_STOP15_RC</ffdc>
+ <ffdc>DEADMAN_TIMEOUT_REASON</ffdc>
<ffdc>CORE_TARGET</ffdc>
<ffdc>PU_OCB_OCI_OCCFLG__PU_OCB_OCI_CCSR</ffdc>
<ffdc>PU_OCB_OCI_QCSR__PU_OCB_OCI_QSSR</ffdc>
@@ -84,6 +70,10 @@
<ffdc>CME_LR__SPRG0</ffdc>
<ffdc>CME_SRR0__SRR1</ffdc>
<callout>
+ <procedure>CODE</procedure>
+ <priority>HIGH</priority>
+ </callout>
+ <callout>
<procedure>LVL_SUPPORT</procedure>
<priority>LOW</priority>
</callout>
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