diff options
Diffstat (limited to 'src/import/chips/p9/procedures/xml/attribute_info')
8 files changed, 4178 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml new file mode 100644 index 00000000..724a5c97 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -0,0 +1,184 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- + XML file specifying HWPF attributes. + These are example Chip EC Feature attributes that specify chip features + based on the EC level of a chip +--> + +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_CORE_TRACE_SCOMABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Returns true if the core trace arrays are dumpable via SCOM. + Nimbus EC 0x20 or greater + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>GREATER_THAN_OR_EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_TEST1</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + Returns if a chip contains the TEST1 feature. True if either: + Centaur EC 10 + Cumulus EC greater than 30 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CENTAUR</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x30</value> + <test>GREATER_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_TEST2</id> + <targetType>TARGET_TYPE_PROC_CHIP, TARGET_TYPE_MEMBUF_CHIP</targetType> + <description> + Returns if a chip contains the TEST2 feature. True if: + Murano EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nimbus DD1 for differentiating present/functional targets. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 attribute for assigning flushvalues to root_ctrl and perv_ctrl registers. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 update : Flush mode not initiated for N3. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Sdis_n set or clear : flushing LCBES condition woraround. True if: + Nimbus EC less than 20 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + <!-- ******************************************************************** --> + <attribute> + <id>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + DD1 only: disable local clock gating VITAL. This is used by the + procedure for p9_sbe_tp_chiplet_init1 and p9_Sbe_chiplet_reset. + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_NIMBUS</name> + <ec> + <value>0x20</value> + <test>LESS_THAN</test> + </ec> + </chip> + </chipEcFeature> + </attribute> +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml new file mode 100644 index 00000000..11c98683 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/core_attributes.xml @@ -0,0 +1,61 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/core_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- $Id: proc_pll_ring_attributes.xml,v 1.17 2014/11/13 20:14:02 szhong Exp $ --> +<!-- proc_pll_ring_attributes.xml --> +<attributes> + <attribute> + <id>ATTR_CORE_REPR_RING</id> + <targetType>TARGET_TYPE_CORE</targetType> + <description> + </description> + <valueType>uint32</valueType> + <platInit/> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CORE_TIME_RING</id> + <targetType>TARGET_TYPE_CORE</targetType> + <description> + </description> + <valueType>uint32</valueType> + <platInit/> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_CORE_GPTR_RING</id> + <targetType>TARGET_TYPE_CORE</targetType> + <description> + </description> + <valueType>uint32</valueType> + <platInit/> + <writeable/> + <persistRuntime/> + </attribute> + <!-- ********************************************************************* --> +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml new file mode 100644 index 00000000..c3bd81b8 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -0,0 +1,1158 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!--nest_attributes.xml--> +<attributes> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_PB_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of a processor's nest mesh clock, in MHz. + This is the same for all chips in the system. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <writeable/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_A_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of a processor's A link clocks, in MHz. + This is the same for all chips in the system. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_X_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of a processor's X link clocks, in MHz. + This is the same for all chips in the system. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_CORE_FLOOR_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The lowest frequency that a core can be set to in MHz. + This is the same for all cores in the system. + Provided by the MVPD #V and is calculated as the max of the + Power Save frequencies. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_CORE_NOMINAL_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The nominal core frequency in MHz. + This is the same for all cores in the system. + Provided by the #V bucket of module VPD. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_CORE_CEILING_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The maximum core frequency in MHz. + This is the same for all cores in the system. + Provided by the #V bucket of module VPD and is calculated + as the minimum of the turbo frequencies. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PM_SAFE_FREQUENCY_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Frequency (in MHz) to move to if the Power Management function fails. + This is the same for all cores in the system. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_FREQ_PCIE_MHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + The frequency of a processor's PCI-e bus in MHz. + This is the same for all PCI-e busses in the system. + Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_ASYNC_SAFE_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Set to force all fabric asynchronous boundary crossings into safe mode. + </description> + <valueType>uint8</valueType> + <enum> + PERFORMANCE_MODE = 0x0, + SAFE_MODE = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_BUS_WIDTH</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP A bus width. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + 2_BYTE = 0x01, + 4_BYTE = 0x02 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_BUS_WIDTH</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP X bus width. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + 2_BYTE = 0x01, + 4_BYTE = 0x02 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CORE_FLOOR_RATIO</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP core floor/nest frequency ratio + </description> + <valueType>uint8</valueType> + <enum> + RATIO_8_8 = 0x0, + RATIO_7_8 = 0x1, + RATIO_6_8 = 0x2, + RATIO_5_8 = 0x3, + RATIO_4_8 = 0x4, + RATIO_2_8 = 0x5 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CORE_CEILING_RATIO</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP core celing/nest frequency ratio + </description> + <valueType>uint8</valueType> + <enum> + RATIO_8_8 = 0x0, + RATIO_7_8 = 0x1, + RATIO_6_8 = 0x2, + RATIO_5_8 = 0x3, + RATIO_4_8 = 0x4, + RATIO_2_8 = 0x5 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_PUMP_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP Fabric broadcast scope configuration. + CHIP_IS_NODE = MODE1 = default + CHIP_IS_GROUP = MODE2 + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + CHIP_IS_NODE = 0x01, + CHIP_IS_GROUP = 0x02 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CCSM_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP topology configuration. + 0 = default = 1 or 2 hop topology (PHYP image spans system) + 1 = 3 hop topology (PHYP image spans group). + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_OPTICS_CONFIG_MODE</id> + <targetType>TARGET_TYPE_OBUS</targetType> + <description> + Per-link optics configuration + 0 = default = SMP + 1 = CAPI 2.0 + 2 = NV 2.0 + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + SMP = 0x0, + CAPI = 0x1, + NV = 0x2 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_SMP_OPTICS_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP optics mode. + 0 = default = Optics_is_X_bus + 1 = Optics_is_A_bus + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + OPTICS_IS_X_BUS = 0x0, + OPTICS_IS_A_BUS = 0x1 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Per-link optics configuration + 0 = default = SMP + 1 = CAPI 2.0 + 2 = NV 2.0 + </description> + <valueType>uint8</valueType> + <enum> + SMP = 0x0, + CAPI = 0x1, + NV = 0x2 + </enum> + <array>4</array> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CAPI_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor CAPI attachement protocol mode. + 0 = default = no: SMPA CAPI attachement + 1 = yes: SMPA CAPI attachement + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_ADDR_BAR_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor memory map configuration. + 0 = default = large system address map + 1 = small system address map + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + LARGE_SYSTEM = 0x0, + SMALL_SYSTEM = 0x1 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_SYSTEM_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Logical fabric system ID associated with this chip.Provided by the MRW. + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_GROUP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Logical fabric group ID associated with this chip. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CHIP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Logical fabric chip ID associated with this chip. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_SYSTEM_MASTER_CHIP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if the given chip should serve as the fabric system master. + </description> + <valueType>uint8</valueType> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_GROUP_MASTER_CHIP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if the given chip should serve as the fabric group master. + </description> + <valueType>uint8</valueType> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric X link on this chip, specifies whether or not the chip at the + receiving end of the link is present and configured + </description> + <valueType>uint8</valueType> + <array>7</array> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric A link on this chip, specifies whether or not the chip at the + receiving end of the link is present and configured + </description> + <valueType>uint8</valueType> + <array>4</array> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_ATTACHED_CHIP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric X link on this chip, specifies the fabric ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>7</array> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_ATTACHED_LINK_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric X link on this chip, specifies the link ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>7</array> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric A link on this chip, specifies the fabric ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>4</array> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_ATTACHED_LINK_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric A link on this chip, specifies the link ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>4</array> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_AGGREGATE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if X links on this chip should be configured in aggregate mode. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_ADDR_DIS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if link should be used to carry data only (in aggregate configurations). + Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint8</valueType> + <array>7</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_LINK_DELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Average of local/remote end link delay counter values. + Used to designate coherent link in aggregate configurations. + Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint32</valueType> + <array>7</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_AGGREGATE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if A links on this chip should be configured in aggregate mode. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_ADDR_DIS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if link should be used to carry data only (in aggregate configurations). + Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint8</valueType> + <array>4</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_LINK_DELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Average of local/remote end link delay counter values. + Used to designate coherent link in aggregate configurations. + Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint32</valueType> + <array>4</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_GB_PERCENTAGE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Guardband percentage to apply to baseline epsilon calculations + Set by p9_fbc_eff_config. + </description> + <valueType>int8</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_TABLE_TYPE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor epsilon table type. + Used to calculate the processor nest epsilon register values. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <enum> + EPS_TYPE_LE = 0x01, + EPS_TYPE_HE = 0x02 + </enum> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_READ_CYCLES_T0</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Calculated read tier0 epsilon protection count. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_READ_CYCLES_T1</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Calculated read tier1 epsilon protection count. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_READ_CYCLES_T2</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Calculated read tier2 epsilon protection count. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_WRITE_CYCLES_T1</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Calculated write tier1 epsilon protection count. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_EPS_WRITE_CYCLES_T2</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Calculated write tier2 epsilon protection count. + </description> + <valueType>uint32</valueType> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_DMI_REFCLOCK_SWIZZLE</id> + <targetType>TARGET_TYPE_MCS</targetType> + <description>Define DMI Ref clock/Swizzle for Centaur. + Provided by the MRW</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_SYSTEM_IPL_PHASE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Define context for current phase of system IPL. + </description> + <valueType>uint8</valueType> + <enum>HB_IPL = 0x1,HB_RUNTIME = 0x2,CACHE_CONTAINED = 0x4, CHIP_CONTAINED = 0x8</enum> + <persistRuntime/> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + p9_sbe_attr_setup.C --> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_IS_MPIPL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Indicates if current IPL is memory-preserving + </description> + <valueType>uint8</valueType> + <enum> + FALSE = 0x0, + TRUE = 0x1 + </enum> + <platInit/> + <!-- TODO: Story 155081 + Not supposed to be writeable, PPE needs to resolve this issue in + sberegaccess.C --> + <writeable/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>XSCOM BAR base address offset + creator: platform + consumer: p9_sbe_scominit + firmware notes: + Defines 16GB range (size implied) mapped for XSCOM usage + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- RA bits 22:29 + (excludes system/memory select/group/chip fields) + </description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>LPC BAR base address offset + creator: platform + consumer: p9_sbe_scominit + firmware notes: + Defines 4GB range (size implied) mapped for LPC usage + Attribute holds offset (relative to chip MMIO origin) to program into + chip address range field of BAR -- RA bits 22:31 + (excludes system/memory select/group/chip fields) + </description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MEM_MIRROR_PLACEMENT_POLICY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Define placement policy/scheme for non-mirrored/mirrored memory + layout + NORMAL = non-mirrored start: 0, mirrored start: 1024TB + FLIPPED = mirrored start: 0, non-mirrored start: 512TB + Set by platform. + Used by mss_eff_grouping. + </description> + <valueType>uint8</valueType> + <enum> + NORMAL = 0x0, + FLIPPED = 0x1 + </enum> + <platInit/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MEM_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The location where the stacking of non-mirrored memory groups + of the chip starts. This address is determined in a fixed + manner from the chip's position in the fabric topology (i.e. + each chip will consume a fixed portion of the system address + map). + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MEM_BASES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The address where each memory group starts in the non-mirrored + memory groups stack. This address is determined by the memory + grouping process based on the sizes of the memory groups formed + in each processor. + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MEM_SIZES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The memory size of each non-mirrored memory group in the + non-mirrored memory groups stack. This size is determined by + the memory grouping process based on the amount of memory + behind the ports that are grouped together. + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_MIRROR_BASE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The location where the stacking of mirrored memory groups + of the chip starts. This address is determined in a fixed + manner from the chip's position in the fabric topology (i.e. + each chip will consume a fixed portion of the system address + map). + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MIRROR_BASES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The address where each memory group starts in the mirrored + memory groups stack. This address is determined by + the memory grouping process based on the sizes of the memory + groups formed in each processor. + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MIRROR_SIZES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The memory size of each memory group in the mirrored memory + groups stack. This size is determined by the memory grouping + process based on the amount of memory behind the ports that are + grouped together. + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MSS_INTERLEAVE_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Used in the setting of groups. It is a bit vector. If the value + BITWISE_AND 0x01 = 0x01 then groups of 1 are enabled, + if the value BITWISE_AND 0x02 = 0x02, then groups of 2 are possible, + if the value BITWISE_AND 0x04 = 0x04, then group of 3 are possible, + if the value BITWISE_AND 0x08 = 0x08, then groups of 4 are possible, + if the value BITWISE_AND 0x20 = 0x20, then groups of 6 are possible, + if the value BITWISE_AND 0x80 = 0x80, then groups of 8 are possible. + If no groups can formed according to this input, then an error will + be thrown. + Provided by the MRW + </description> + <valueType>uint8</valueType> + <platInit/> + <odmVisable/> + <odmChangeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MSS_MEM_MC_IN_GROUP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + An 8 bit vector that would be a designation of which MC (Nimbus MCS or + Cumulus MI) are involved in the group. + So the bits would represent + Nimbus Cumulus + Bit 0 MCS0 MI0 + Bit 1 MCS1 MI1 + ..... + Bit 7 MCS7 MI7 + Set by p9_mss_eff_grouping + </description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array>8</array> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MSS_MCS_GROUP_32</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + creator:- mss_eff_grouping + consumer:- mss_setup_bars + Data Structure from eff grouping to setup bars to help determine + different groups + Non-Mirroring array[0-7] [0.17]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of non-mirroring; + 3-- Base address; 4-11-- PortID number in group; + 12-- Alt Memory valid(0); 13-- Alt Memory valid (1); + 14-- Alt Group size (0); 15-- Alt Group size(1); + 16-- Alt Base address (0); 17-- Alt Base address (1); + + 13-- Alternate Group Size; 14-- Alternate Base address + Mirroring array[8-15] [0:17]: 0-- Port size; 1-- No of ports in group; 2-- Total group size of mirroring; + 3-- Base address; 4-11-- PortID number; + 12-- Alt Memory valid(0); 13-- Alt Memory valid (1); + 14-- Alt Group size (0); 15-- Alt Group size(1); + 16-- Alt Base address (0); 17-- Alt Base address (1); + Measured in GB + </description> + <valueType>uint32</valueType> + <array>16,18</array> + <writeable/> + <odmVisable/> + <odmChangeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MSS_MEM_IPL_COMPLETE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Creator:- mss_setup_bars + A numerical number indicating if the memory procedures are complete. + written by mss_setup_bars when the bars are now functional in the + processor. + </description> + <valueType>uint8</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <persistRuntime/> + <initToZero/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_MRW_HW_MIRRORING_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + TRUE : HW mirroring is enabled. + FALSE : HW mirroring is disabled. + Provided by the MRW. + </description> + <valueType>uint8</valueType> + <platInit/> + <enum>FALSE = 0, TRUE = 1</enum> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_NHTM_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The base address where the NHTM traces start. They are + calculated based on the NHTM trace size requested by user. + This address in memory will be the location where NHTM0/1 + traces are output. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars and p9_htm_setup. + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_NHTM_BAR_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The amount of memory a user can reserve to store NHTM traces. + This amount will be used to store both NHTM0 and NHTM1 traces. + Used by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <enum> + 256_GB = 0x0000004000000000, + 128_GB = 0x0000002000000000, + 64_GB = 0x0000001000000000, + 32_GB = 0x0000000800000000, + 16_GB = 0x0000000400000000, + 8_GB = 0x0000000200000000, + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + ZERO = 0x0000000000000000 + </enum> + <initToZero/> + <writeable/> + <persistRuntime/> +</attribute> + +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_CHTM_BAR_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The base addresses where the CHTM traces start. They are + calculated based on the CHTM trace sizes requested by users. + There are 24 different CHTM regions, thus 24 different sizes. + Each region is to store HTM trace for a core. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars. + </description> + <valueType>uint64</valueType> + <array>24</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_CHTM_BAR_SIZES</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The amount of memory a user can reserve to store CHTM traces. + There are 24 cores, thus 24 different sizes. + Used by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <enum> + 256_GB = 0x0000004000000000, + 128_GB = 0x0000002000000000, + 64_GB = 0x0000001000000000, + 32_GB = 0x0000000800000000, + 16_GB = 0x0000000400000000, + 8_GB = 0x0000000200000000, + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + ZERO = 0x0000000000000000 + </enum> + <array>24</array> + <initToZero/> + <writeable/> + <persistRuntime/> +</attribute> + +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_OCC_SANDBOX_BASE_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The base address where the OCC sandbox starts. It is + calculated based on the OCC sandbox size requested by users. + Set by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_OCC_SANDBOX_SIZE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The amount of memory a user can reserve to store OCC sandbox + functions. + Used by p9_mss_eff_grouping. + </description> + <valueType>uint64</valueType> + <enum> + 256_GB = 0x0000004000000000, + 128_GB = 0x0000002000000000, + 64_GB = 0x0000001000000000, + 32_GB = 0x0000000800000000, + 16_GB = 0x0000000400000000, + 8_GB = 0x0000000200000000, + 4_GB = 0x0000000100000000, + 2_GB = 0x0000000080000000, + 1_GB = 0x0000000040000000, + 512_MB = 0x0000000020000000, + 256_MB = 0x0000000010000000, + 128_MB = 0x0000000008000000, + 64_MB = 0x0000000004000000, + 32_MB = 0x0000000002000000, + 16_MB = 0x0000000001000000, + ZERO = 0x0000000000000000 + </enum> + <initToZero/> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MEM_BASES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The actual non-mirrored base addresses of the groups formed + by the memory grouping process. These values correspond to + the BAR programming and would be acknowleged on the fabric. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars. + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_MEM_SIZES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The actual non-mirrored memory sizes of the groups formed + by the memory grouping process. These values correspond to + the BAR programming. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars. + </description> + <valueType>uint64</valueType> + <array>8</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_MIRROR_BASES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The actual mirrored base addresses of the groups formed + by the memory grouping process. These values correspond to + the BAR programming and would be acknowleged on the fabric. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars. + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> +<attribute> + <id>ATTR_PROC_MIRROR_SIZES_ACK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> The actual mirrored memory sizes of the groups formed + by the memory grouping process. These values correspond to + the BAR programming. + Set by p9_mss_eff_grouping. + Used by p9_setup_bars. + </description> + <valueType>uint64</valueType> + <array>4</array> + <writeable/> + <persistRuntime/> +</attribute> +<!-- ********************************************************************* --> + +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml new file mode 100644 index 00000000..9caa1a92 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml @@ -0,0 +1,52 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_cache_contained_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<attributes> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_RUNN_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Set to indicate clock-start/instruction execution in cache-contained + mode will be managed by runn + Provided by: platform (FW platforms init to OFF) + </description> + <valueType>uint8</valueType> + <platInit/> + <enum>OFF=0, ON=1</enum> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_RUNN_CYCLE_COUNT</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description> + Number of clock cycles to execute in runn mode + Consumed by: p9_runn HWP (Cronus platform only, cache-contained mode) + Provided by: platform (FW platforms init to 0) + </description> + <valueType>uint64</valueType> + <platInit/> +</attribute> +<!-- ********************************************************************** --> +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml new file mode 100644 index 00000000..4972e342 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -0,0 +1,525 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- p9_sbe_attributes.xml --> +<!-- This file defines the subset of attributes from the larger pool of --> +<!-- defined attributes that will be included in the SBE platform. --> +<!-- Additionally, build time initial values can also be optionally --> +<!-- defined. --> +<entries> + <!-- ********************************************************************* --> + <entry> + <name>ATTR_PIBMEM_REPAIR0</name> + <value>0x0000000000000000</value> + </entry> + <entry> + <name>ATTR_PIBMEM_REPAIR1</name> + <value>0x0000000000000000</value> + </entry> + <entry> + <name>ATTR_PIBMEM_REPAIR2</name> + <value>0x0000000000000000</value> + </entry> + <entry> + <name>ATTR_I2C_BUS_DIV_REF</name> + <value>0x0001</value> + </entry> + <entry> + <name>ATTR_FUNCTIONAL_EQ_EC_VALID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_EQ_GARD</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_EC_GARD</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_I2C_BUS_DIV_REF_VALID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_IS_MPIPL</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_BOOT_FREQUENCY_VALID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_NEST_PLL_BUCKET</name> + <value>0x05</value> + </entry> + <entry> + <name>ATTR_BOOT_FREQ_MULT</name> + <value>0x00B4</value> + </entry> + <entry> + <name>ATTR_HWP_CONTROL_FLAGS_VALID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_SYSTEM_IPL_PHASE</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_RISK_LEVEL</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_DISABLE_HBBL_VECTORS</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_CHIP_SELECTION_VALID</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_CHIP_SELECTION</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_NODE_POS</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_CHIP_POS</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT8_1</name> + <value>0x8</value> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT8_2</name> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT32_1</name> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT32_2</name> + <value>0xaffeaffe</value> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT64_1</name> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT64_2</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT8_1</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT8_2</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT32_1</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT32_2</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT64_1</name> + </entry> + <entry> + <name>ATTR_SCRATCH_INT64_2</name> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT32_ARRAY</name> + </entry> + <entry> + <name>ATTR_SCRATCH_UINT32_PERV_ARRAY</name> + </entry> + <entry> + <name>ATTR_REPR_RING</name> + <value>0xcafe</value> + <value>0xdead</value> + </entry> + <entry> + <name>ATTR_TIME_RING</name> + </entry> + <entry> + <name>ATTR_GPTR_RING</name> + <value>0xcafe</value> + <value>0xaffe</value> + </entry> + <entry> + <name>ATTR_PLL_RING</name> + </entry> + <entry> + <name>ATTR_CORE_REPR_RING</name> + </entry> + <entry> + <name>ATTR_CORE_TIME_RING</name> + </entry> + <entry> + <name>ATTR_CORE_GPTR_RING</name> + </entry> + <entry> + <name>ATTR_L2_REPR_RING</name> + </entry> + <entry> + <name>ATTR_L2_TIME_RING</name> + <value>0xcafe</value> + <value>0xaffe</value> + </entry> + <entry> + <name>ATTR_L2_GPTR_RING</name> + </entry> + <entry> + <name>ATTR_L3_REPR_RING</name> + </entry> + <entry> + <name>ATTR_L3_TIME_RING</name> + <value>0xcafe</value> + <value>0xaffe</value> + </entry> + <entry> + <name>ATTR_L3_GPTR_RING</name> + </entry> + <entry> + <name>ATTR_DPLL_RING</name> + </entry> + <entry> + <name>ATTR_CHIP_UNIT_POS</name> + <value>0x01</value> <!-- PERV --> + <value>0x02</value> <!-- N0 --> + <value>0x03</value> <!-- N1 --> + <value>0x04</value> <!-- N2 --> + <value>0x05</value> <!-- N3 --> + <value>0x06</value> <!-- XB --> + <value>0x07</value> <!-- MC01 --> + <value>0x08</value> <!-- MC23 --> + <value>0x09</value> <!-- OB0 --> + <value>0x0A</value> <!-- OB1 --> + <value>0x0B</value> <!-- OB2 --> + <value>0x0C</value> <!-- OB3 --> + <value>0x0D</value> <!-- PCI0 --> + <value>0x0E</value> <!-- PCI1 --> + <value>0x0F</value> <!-- PCI2 --> + <value>0x10</value> <!-- EP0 --> + <value>0x11</value> <!-- EP1 --> + <value>0x12</value> <!-- EP2 --> + <value>0x13</value> <!-- EP3 --> + <value>0x14</value> <!-- EP4 --> + <value>0x15</value> <!-- EP5 --> + <value>0x20</value> <!-- EC00 --> + <value>0x21</value> <!-- EC01 --> + <value>0x22</value> <!-- EC02 --> + <value>0x23</value> <!-- EC03 --> + <value>0x24</value> <!-- EC04 --> + <value>0x25</value> <!-- EC05 --> + <value>0x26</value> <!-- EC06 --> + <value>0x27</value> <!-- EC07 --> + <value>0x28</value> <!-- EC08 --> + <value>0x29</value> <!-- EC09 --> + <value>0x2A</value> <!-- EC10 --> + <value>0x2B</value> <!-- EC11 --> + <value>0x2C</value> <!-- EC12 --> + <value>0x2D</value> <!-- EC13 --> + <value>0x2E</value> <!-- EC14 --> + <value>0x2F</value> <!-- EC15 --> + <value>0x30</value> <!-- EC16 --> + <value>0x31</value> <!-- EC17 --> + <value>0x32</value> <!-- EC18 --> + <value>0x33</value> <!-- EC19 --> + <value>0x34</value> <!-- EC20 --> + <value>0x35</value> <!-- EC21 --> + <value>0x36</value> <!-- EC22 --> + <value>0x37</value> <!-- EC23 --> + </entry> + + <entry> + <name>ATTR_BACKUP_SEEPROM_SELECT</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_MC_SYNC_MODE</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_BOOT_FLAGS</name> + <value>0x80000000</value> + </entry> + <entry> + <name>ATTR_BOOT_FREQ</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_VCS_BOOT_VOLTAGE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_VDD_BOOT_VOLTAGE</name> + <value>0x0</value> + </entry> + <entry> + <!-- The values here are per pervasive chiplet in the order of the chiplet + numbers Bit 3 (in the 16-bit representation) is used to indicate + partial good. If this bit is 1, the region is bad, else it is good. + Bits 0,1,2 are don't care. For nimbus, pervasive chiplets 10 and 11 are + not used (OB1 and OB2), therefore the value for them is 0xFFFF --> + <name>ATTR_PG</name> + <value>0xE07D</value> <!-- PERV --> + <value>0xE03F</value> <!-- N0 --> + <value>0xE03F</value> <!-- N1 --> + <value>0xE03F</value> <!-- N2 --> + <value>0xE01F</value> <!-- N3 --> + <value>0xE00D</value> <!-- XB --> + <value>0xE0FD</value> <!-- MC01 --> + <value>0xE0FD</value> <!-- MC23 --> + <value>0xE1FD</value> <!-- OB0 --> + <value>0xFFFF</value> <!-- OB1 --> + <value>0xFFFF</value> <!-- OB2 --> + <value>0xE1FD</value> <!-- OB3 --> + <value>0xE1FD</value> <!-- PCI0 --> + <value>0xE0FD</value> <!-- PCI1 --> + <value>0xE07D</value> <!-- PCI2 --> + <value>0xE001</value> <!-- EP0 --> + <value>0xE001</value> <!-- EP1 --> + <value>0xE001</value> <!-- EP2 --> + <value>0xE288</value> <!-- EP3 --> + <value>0xE001</value> <!-- EP4 --> + <value>0xE001</value> <!-- EP5 --> + <value>0xE1FF</value> <!-- EC00 --> + <value>0xE1FF</value> <!-- EC01 --> + <value>0xE1FF</value> <!-- EC02 --> + <value>0xE1FF</value> <!-- EC03 --> + <value>0xE1FF</value> <!-- EC04 --> + <value>0xE1FF</value> <!-- EC05 --> + <value>0xE1FF</value> <!-- EC06 --> + <value>0xE1FF</value> <!-- EC07 --> + <value>0xE1FF</value> <!-- EC08 --> + <value>0xE1FF</value> <!-- EC09 --> + <value>0xE1FF</value> <!-- EC10 --> + <value>0xE1FF</value> <!-- EC11 --> + <value>0xE1FF</value> <!-- EC12 --> + <value>0xE1FF</value> <!-- EC13 --> + <value>0xE1FF</value> <!-- EC14 --> + <value>0xE1FF</value> <!-- EC15 --> + <value>0xE1FF</value> <!-- EC16 --> + <value>0xE1FF</value> <!-- EC17 --> + <value>0xE1FF</value> <!-- EC18 --> + <value>0xE1FF</value> <!-- EC19 --> + <value>0xE1FF</value> <!-- EC20 --> + <value>0xE1FF</value> <!-- EC21 --> + <value>0xE1FF</value> <!-- EC22 --> + <value>0xE1FF</value> <!-- EC23 --> + </entry> + <entry> + <name>ATTR_ADU_XSCOM_BAR_BASE_ADDR</name> + <value>0x000603FC00000000</value> + </entry> + <entry> + <name>ATTR_LPC_BASE_ADDR</name> + <value>0x0006030000000000</value> + </entry> + <entry> + <name>ATTR_SUN_ID</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_PROC_SBE_MASTER_CHIP</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_PROC_FABRIC_SYSTEM_ID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_PROC_FABRIC_GROUP_ID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_PROC_FABRIC_CHIP_ID</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_PROC_FABRIC_ADDR_BAR_MODE</name> + <value>0x01</value> + </entry> + <entry> + <name>ATTR_MEM_MIRROR_PLACEMENT_POLICY</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_SBE_BOOTLOADER_OFFSET</name> + <value>0x200000</value> + </entry> + <entry> + <name>ATTR_HOSTBOOT_HRMOR_OFFSET</name> + <value>0x8000000</value> + </entry> + <entry> + <name>ATTR_SYS_FORCE_ALL_CORES</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_MASTER_CORE</name> + </entry> + <entry> + <name>ATTR_MASTER_EX</name> + </entry> + <entry> + <name>ATTR_PNOR_SIZE</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_PNOR_BOOT_SIDE</name> + <value>0x00</value> + </entry> + <entry> + <name>ATTR_SBE_BOOT_SIDE</name> + <value>0x00</value> + </entry> + <!-- TODO we need to change this once the absolute address is known --> + <entry> + <name>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</name> + <value>0x48000000</value> + </entry> + <entry> + <name>ATTR_CLOCK_PLL_MUX</name> + <value>0x80010800</value> + </entry> + <entry> + <name>ATTR_CLOCK_PLL_MUX0</name> + <value>0x3</value> + </entry> + <entry> + <name>ATTR_PROC_EPS_READ_CYCLES_T0</name> + <value>0x00000FFF</value> + </entry> + <entry> + <name>ATTR_PROC_EPS_READ_CYCLES_T1</name> + <value>0x00000FFF</value> + </entry> + <entry> + <name>ATTR_PROC_EPS_READ_CYCLES_T2</name> + <value>0x00000FFF</value> + </entry> + <entry> + <name>ATTR_PROC_EPS_WRITE_CYCLES_T1</name> + <value>0x00000FFF</value> + </entry> + <entry> + <name>ATTR_PROC_EPS_WRITE_CYCLES_T2</name> + <value>0x00000FFF</value> + </entry> + <entry> + <name>ATTR_SECURITY_MODE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_SECURITY_ENABLE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_PFET_OFF_CONTROLS</name> + <value>0x00000000</value> + </entry> + <entry> + <name>ATTR_OBUS_RATIO_VALUE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_ECID</name> + </entry> + <entry> + <name>ATTR_RUNN_MODE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_SS_FILTER_BYPASS</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_CP_FILTER_BYPASS</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_IO_FILTER_BYPASS</name> + <value>0x1</value> + </entry> + <entry> + <name>ATTR_VDM_ENABLE</name> + <value>0x0</value> + </entry> + <!-- See chip_attributes.xml for a description of ATTR_EC --> + <entry> + <name>ATTR_EC</name> + <!-- The value needs to be changed as per the EC level --> + <value>0x10</value> + </entry> + <!-- See chip_attributes.xml for a description of ATTR_NAME --> + <entry> + <name>ATTR_NAME</name> + <!-- NIMBUS --> + <value>0x5</value> + </entry> +<!-- +This is an example of how to add a CHIP EC feature attribute to this file +The virtual tag indicates to the SBE plat to not attach storage in the +attribute tank + <entry> + <name>ATTR_CHIP_EC_FEATURE_TEST1</name> + <virtual/> + </entry> +--> + +<!-- Pervasive EC attributes --> + <entry> + <name>ATTR_CHIP_EC_FEATURE_FSI_GP_SHADOWS_OVERWRITE</name> + <virtual/> + </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_N3_FLUSH_MODE</name> + <virtual/> + </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_VITL_CLK_SETUP</name> + <virtual/> + </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_SDISN_SETUP</name> + <virtual/> + </entry> + <entry> + <name>ATTR_CHIP_EC_FEATURE_VITL_CLOCK_GATING</name> + <virtual/> + </entry> + + <entry> + <name>ATTR_PROC_XSCOM_BAR_BASE_ADDR_OFFSET</name> + <value>0x000003FC00000000</value> + </entry> + + <entry> + <name>ATTR_PROC_LPC_BAR_BASE_ADDR_OFFSET</name> + <value>0x000003FB00000000</value> + </entry> + + +</entries> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml new file mode 100644 index 00000000..7330b468 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml @@ -0,0 +1,89 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/p9_sbe_load_bootloader_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- This is an automatically generated file. --> +<!-- File: nest_attributes.xml. --> +<!-- XML file specifying attributes used by HW Procedures. --> +<!-- Attributes are taken from model nest --> +<!--nest_attributes.xml--> +<attributes> +<attribute> + <id>ATTR_SBE_BOOTLOADER_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Defines offset to be applied to SBE bootloader installation + this will be added with the base address and hostboot HRMOR offset to get the target + base address</description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +<attribute> + <id>ATTR_HOSTBOOT_HRMOR_OFFSET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Defines offset to be applied to SBE bootloader installation + this will be added with the bootloader offset and the base address to get the + target base addres</description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +<attribute> + <id>ATTR_PNOR_SIZE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Defines size of PNOR that will be put into the exception vector if written</description> + <valueType>uint16</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +<attribute> + <id>ATTR_SBE_BOOT_SIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Defines sbe boot side that will be put into the exception vector if written</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +<attribute> + <id>ATTR_PNOR_BOOT_SIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Defines boot side of PNOR that will be put into the exception vector if written</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +<attribute> + <id>ATTR_SBE_HBBL_EXCEPTION_INSTRUCT</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Instruction for exception vector that will be put into the exception vector if not 0</description> + <valueType>uint32</valueType> + <persistRuntime/> + <platInit/> + <initToZero/> +</attribute> +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml new file mode 100644 index 00000000..22a063c5 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -0,0 +1,683 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- This is an automatically generated file. --> +<!-- File: pervasive_attributes.xml. --> +<!-- XML file specifying attributes used by HW Procedures. Attributes are taken from model pervasive --> +<!--pervasive_attributes.xml--> +<attributes> + +<attribute> + <id>ATTR_CLOCK_PLL_MUX</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>setup clock mux settings</description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_CLOCK_PLL_MUX0</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Clock Mux#0 settings</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_I2C_BUS_DIV_REF</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Ref clock I2C bus divider consumed by code running out of OTPROM</description> + <valueType>uint16</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_FUNCTIONAL_EQ_EC_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the validitiy of FW functional EQ/EQ register</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_EQ_GARD</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Capturing EQ Gard value</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_EC_GARD</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Capturing EC Gard Value</description> + <valueType>uint32</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_I2C_BUS_DIV_REF_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the validity of ref clock I2C bus divider consumed by + code running out of OTPROM</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_FW_MODE_FLAGS_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the validity of FW flags. Ex: ISTEP_MODE, + SBE_RUNTIME_MODE, MPIPL_MODE, SP_MODE, SBE_FFDC_ENABLE</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_ISTEP_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates istep IPL</description> + <valueType>uint8</valueType> + <enum>NON_IPL = 0x0,IPL = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SBE_RUNTIME_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates that SBE should go directly to runtime functionality</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_IS_SP_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates whether we are connected to FSP or not</description> + <valueType>uint8</valueType> + <enum>FSP_LESS = 0x0,FSP = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SBE_FFDC_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates whether SBE should collect FFDC</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SBE_INTERNAL_FFDC_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates that the SBE should send back internal FFDC on any + chipOp failure response</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_BOOT_FREQUENCY_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates if BOOT_FREQ_MULT and NEST_PLL_BUCKET + are valid</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_NEST_PLL_BUCKET</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Select Nest I2C and pll setting from one of the supported frequencies</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_BOOT_FREQ_MULT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>EQ boot frequency multiplier</description> + <valueType>uint16</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_HWP_CONTROL_FLAGS_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates if HWP control flags + are valid</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_RISK_LEVEL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven + HWPs</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_DISABLE_HBBL_VECTORS</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>BootLoader HWP flag to not place 12K exception vectors. + This flag is only applicable when security is disabled.</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_CHIP_SELECTION_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates that master/slave, node/chip selection attributes + are valid</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_CHIP_SELECTION</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>master/slave bit</description> + <valueType>uint8</valueType> + <enum>MASTER = 0x0,SLAVE = 0x1</enum> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_NODE_POS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicate the node position in FSP based systems (unused in Spless systems)</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_CHIP_POS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicate the chip position</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SCRATCH6_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicate if scratch reg6 bits are valid</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SCRATCH7_VALID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicate if scratch reg7 bits are valid</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_BACKUP_SEEPROM_SELECT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Set with Primary SEEPROM</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_BOOT_FLAGS</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Switch to using a flag to indicate SEEPROM side SBE</description> + <valueType>uint32</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_BOOT_FREQ_MHZ</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>EQ boot frequency</description> + <valueType>uint32</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_BRANCH_PIBMEM_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_CHIP_REGIONS_TO_ENABLE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint32</valueType> +</attribute> + +<attribute> + <id>ATTR_DEVICE_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_ECID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Bits 0 to 63 of the ECID in array entry 0 and bits 64 to 127 in ECID array entry 1 + Created from running the mss_get_cen_ecid.C + Firmware shares some code with the processor, + so the attribute is named so they can point at a target and have common function.</description> + <valueType>uint64</valueType> + <writeable/> + <odmVisable/> + <odmChangeable/> + <array> 2</array> +</attribute> + +<attribute> + <id>ATTR_I2C_BUS_DIV_NEST</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>I2C Bus speed based on nest freq, ref clock</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_LEN_OF_SEEPROM_DATA</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_MB_BIT_RATE_DIVISOR_PLL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_MB_BIT_RATE_DIVISOR_REFCLK</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_MC_SYNC_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>MC mesh to use Nest mesh or not</description> + <valueType>uint8</valueType> + <persistRuntime/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_PG</id> + <targetType>TARGET_TYPE_PERV</targetType> + <description> + Chiplet Partial good info attribute. Provided by Ring scans. + This should be a direct copy of the data from the PG keyword of VPD. + (Note : the 16-bit vpd data is right-justified into attribute) + </description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_PB_BNDY_DMIPLL_DATA</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Ring image for pb_bndy_dmipll ring creator: platform firmware notes:</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_PB_BNDY_DMIPLL_FOR_DCCAL_DATA</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Ring image for pb_bndy_dmipll ring for DC cal creator: platform firmware notes:</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_PERV_BNDY_PLL_DATA</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Ring image for perv_bndy_pll ring containing filter plls and xb_pll,nest_pll creator: platform firmware notes:</description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_PROC_SBE_MASTER_CHIP</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates if SBE on this chip is serving as hosboot drawer master</description> + <valueType>uint8</valueType> + <enum>FALSE = 0x0,TRUE = 0x1</enum> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SBE_SEEPROM_I2C_DEVICE_ADDRESS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint64</valueType> +</attribute> + +<attribute> + <id>ATTR_SBE_SEEPROM_I2C_PORT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint64</valueType> +</attribute> + +<attribute> + <id>ATTR_START_PIBMEM_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_START_SEEPROM_ADDR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_WAIT_N0</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_WAIT_N1</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_WAIT_N2</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_WAIT_N3</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description></description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SYS_FORCE_ALL_CORES</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Indicate that p9_sbe_select_ex should force selection to ALL good + EX chiplets having good cores even if only a single EX chiplet mode is executed. + </description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_MASTER_CORE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the master boot core chiplet selected by p9_sbe_select_ex. + </description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_MASTER_EX</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Indicates the EX targert associated with the master boot core selected + by p9_sbe_select_ex. + </description> + <valueType>uint8</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SECURITY_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Holds the state of Security Access Bit (SAB)</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SECURITY_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is + Else ATTR_SECURITY_MODE == 0b0, then clear the SAB bit</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_PFET_OFF_CONTROLS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To disable force pfet off control from fuse status</description> + <valueType>uint32</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_OBUS_RATIO_VALUE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>Holds Obus ratio value</description> + <valueType>uint8</valueType> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_PIBMEM_REPAIR0</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Pibmem repair attribute 0</description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + + <attribute> + <id>ATTR_PIBMEM_REPAIR1</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Pibmem repair attribute 1</description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + + <attribute> + <id>ATTR_PIBMEM_REPAIR2</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Pibmem repair attribute 2</description> + <valueType>uint64</valueType> + <persistRuntime/> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SENSEADJ_STEP</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description>IPL for skew adjust and duty cycle adjust</description> + <valueType>uint8</valueType> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_CP_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of CP PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_SS_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of SS PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_IO_FILTER_BYPASS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description>To skip the locking sequence and check for lock of IO PLL</description> + <valueType>uint8</valueType> + <platInit/> +</attribute> + +<attribute> + <id>ATTR_TARGET_HAS_POWER</id> + <targetType>TARGET_TYPE_PERV</targetType> + <description>Functional Target has power</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_TARGET_HAS_CLOCK</id> + <targetType>TARGET_TYPE_PERV</targetType> + <description>Functional Target has clock</description> + <initToZero></initToZero> + <valueType>uint8</valueType> + <writeable/> + <persistRuntime/> +</attribute> + +<attribute> + <id>ATTR_TARGET_IS_SCOMMABLE</id> + <targetType>TARGET_TYPE_PERV</targetType> + <initToZero></initToZero> + <description>Functional Target is scommable</description> + <valueType>uint8</valueType> + <writeable/> + <persistRuntime/> +</attribute> + +</attributes> diff --git a/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml new file mode 100644 index 00000000..164c5ce9 --- /dev/null +++ b/src/import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml @@ -0,0 +1,1426 @@ +<!-- IBM_PROLOG_BEGIN_TAG --> +<!-- This is an automatically generated prolog. --> +<!-- --> +<!-- $Source: import/chips/p9/procedures/xml/attribute_info/pm_plat_attributes.xml $ --> +<!-- --> +<!-- OpenPOWER sbe Project --> +<!-- --> +<!-- Contributors Listed Below - COPYRIGHT 2015,2016 --> +<!-- [+] International Business Machines Corp. --> +<!-- --> +<!-- --> +<!-- Licensed under the Apache License, Version 2.0 (the "License"); --> +<!-- you may not use this file except in compliance with the License. --> +<!-- You may obtain a copy of the License at --> +<!-- --> +<!-- http://www.apache.org/licenses/LICENSE-2.0 --> +<!-- --> +<!-- Unless required by applicable law or agreed to in writing, software --> +<!-- distributed under the License is distributed on an "AS IS" BASIS, --> +<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or --> +<!-- implied. See the License for the specific language governing --> +<!-- permissions and limitations under the License. --> +<!-- --> +<!-- IBM_PROLOG_END_TAG --> +<!-- pm_plat_attributes.xml --> +<!-- --> +<!-- XML file specifying Power Management HWPF attributes. --> +<!-- These attributes are initialized by the platform. --> +<attributes> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_EXTERNAL_VRM_STEPSIZE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <!-- <<<<<<< PROC_CHIP POSSIBLE --> + <description> + Step size (binary in microvolts) to take upon external VRM voltage + transitions. The value set here must take into account where internal + VRMs are enabled or not as, when they are enabled, the step size must + account for the tracking (eg PFET strength recalculation) for the step. + + Consumer: p9_pstate_parameter_block -> + Pstate Parameter Block (PSPB) for PGPE + + Provided by the Machine Readable Workbook after system characterization. + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_EXTERNAL_VRM_STEPDELAY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <!-- <<<<<<< PROC_CHIP POSSIBLE --> + <description> + Step delay (binary in microseconds) after a voltage change + + Consumer: p9_pstate_parameter_block -> + Pstate Parameter Block (PSPB) for PGPE + + Provided by the Machine Readable Workbook after system characterization. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_AVSBUS_FREQUENCY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <!-- <<<<<<< PROC_CHIP POSSIBLE --> + <description> + AVSBus Clock Frequency (binary in KHz) + + Consumer: p9_ocb_init.C + + Overridden by the Machine Readable Workbook. + + If default of 0 is read, HWP will set AVSBus frequency to 1MHz. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDD_AVSBUS_BUSNUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus (0 or 1) which has the core VDD rail VRM + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDN_AVSBUS_BUSNUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus (0 or 1) which has the chip VDN rail VRM + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VCS_AVSBUS_BUSNUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus (0 or 1) which has the chip VCS rail VRM + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDD_AVSBUS_RAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus rail selector number (0 - 15) for the VDD VRM on the bus + defined by ATTR_AVSBUS_VDD_BUSNUM. + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDN_AVSBUS_RAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus rail selector number (0 - 15) for the VDN VRM on the bus + defined by ATTR_AVSBUS_VDN_BUSNUM. + + Producer: Machine Readable Workbook + Consumers: + p9_set_avsbus_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VCS_AVSBUS_RAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the AVSBus rail selector number (0 - 15) for the VCS VRM on the bus + defined by ATTR_AVSBUS_VDN_BUSNUM. + + Producer: Machine Readable Workbook + Consumers: + p9_set_avsbus_voltage (tool); + p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VCS_I2C_BUSNUM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the I2C bus number (0 - 15) that has the VCS VRM. + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool) + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VCS_I2C_RAIL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the I2C rail selector number (0 - 15) for the VCS VRM on the + bus defined by ATTR_VCS_I2C_BUSNUM. + + Producer: Machine Readable Workbook + Consumers: p9_set_evid; + p9_set_voltage (tool) + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDD_BOOT_VOLTAGE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Voltage (binary in 1mV units) to apply to the VDD VRM for booting. Value + chosen is system dependent and is a combination of the part's Vital Product + Data (VPD) (typically the PowerSave value) and the minimum allowed for + correct operation of the fabric bus. + + Producer: p9_setup_evid (first pass) + + Consumer: p9_setup_evid (second pass) + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDN_BOOT_VOLTAGE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Voltage (binary in 1mV units) to apply to the VDN VRM for booting. Value + chosen is system dependent and is a combination of the part's Vital Product + Data (VPD) (typically the PowerSave value) and the minimum allowed for + correct operation of the fabric bus. + + Producer: p9_setup_evid (first pass) + + Consumer: p9_setup_evid (second pass) + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VCS_BOOT_VOLTAGE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Voltage (binary in 1mV units) to apply to the VCS VRM for booting. Value + chosen is system dependent and is a combination of the part's Vital Product + Data (VPD) (typically the PowerSave value) and the minimum allowed for + correct operation of the fabric bus. + + Producer: p9_setup_evid (first pass) + + Consumer: p9_setup_evid (second pass) + </description> + <valueType>uint32</valueType> + <writeable/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SPIPSS_FREQUENCY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + SPIPSS Clock Frequency (binary in KHz) + + Valid range: 500KHz to 2500KHz + + Consumer: p8_pss_init + + Overridden by the Machine Readable Workbook. + + If default of 0 is read, HWP will set SPIPSS frequency to 10MHz. + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_APSS_CHIP_SELECT</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines which of the PSS chip selects (0 or 1) that the APSS is connected + + Provided by the Machine Readable Workbook. + Consumer: p8_pss_init + </description> + <valueType>uint8</valueType> + <enum>NONE = 0xFF, CS0 = 0x00, CS1 = 0x01</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_LOADLINE_VDD_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary microOhms) of the load line from a processor VDD VRM to the + Processor Module pins. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_DISTLOSS_VDD_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary in microOhms) of the VDD distribution loss sense point + to the circuit. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_VRM_VOFFSET_VDD_UV</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Offset voltage (binary in microvolts) to apply to the VDD VRM distribution + to the processor module. This value is applied to each processor instance. + + Note: no loadline may be present in the system; thus, a value of 0 is + legal. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_LOADLINE_VDN_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary microOhms) of the load line from a processor VDN VRM to + the Processor Module pins. This value is applied to each processor + instance. + + Note: no loadline may be present in the system; thus, a value of 0 is + legal. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_DISTLOSS_VDN_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary in microOhms) of the VDN distribution loss sense point + to the circuit. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_VRM_VOFFSET_VDN_UV</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Offset voltage (binary in microvolts) to apply to the VDN VRM distribution + to the processor module. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_LOADLINE_VCS_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary microOhms) of the load line from a processor VCS VRM to + the Processor Module pins. This value is applied to each processor + instance. + + Note: no loadline may be present in the system; thus, a value of 0 is + legal. + + Producer: Machine Readable Workbook (per the power subsystem design) + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_R_DISTLOSS_VCS_UOHM</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Impedance (binary in microOhms) of the VCS distribution loss sense point + to the circuit. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (via the power subsystem design per + system) + + Consumer: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PROC_VRM_VOFFSET_VCS_UV</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Offset voltage (binary in microvolts) to apply to the VCS VRM distribution + to the processor module. This value is applied to each processor instance. + + Producer: Machine Readable Workbook (via the power subsystem design per + system) + + Consumer: FSP + </description> + <valueType>uint32</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_FREQ_BIAS_ULTRATURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + UltraTurbo Frequency Bias - % of bias (signed twos complement in 0.5 + percent steps) used in calculating the frequency associated with a Pstate + - both Global and Local. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_FREQ_BIAS_TURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Turbo Frequency Bias - % of bias (signed twos complement in 0.5 percent + steps) used in calculating the frequency associated with a Pstate - both + Global and Local. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_FREQ_BIAS_NOMINAL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nominal Frequency Bias - % of bias (signed twos complement in 0.5 percent + steps) used in calculating the frequency associated with a Pstate - both + Global and Local. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_FREQ_BIAS_POWERSAVE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + PowerSave Frequency Bias - % of bias (signed twos complement in 0.5 percent + steps) used in calculating the frequency associated with a Pstate - both + Global and Local. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VDD_BIAS_ULTRATURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + UltraTurbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 + percent steps) that is applied to the UltraTurbo VPD point used in + calculating the Global Pstate values. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VDD_BIAS_TURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Turbo VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent + steps) that is applied to the UltraTurbo VPD point used in calculating the + Global Pstate values. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VDD_BIAS_NOMINAL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Nominal VDD Voltage Bias - % of bias (signed twos complement in 0.5 percent + steps) that is applied to the UltraTurbo VPD point used in calculating the + Global Pstate values. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VDD_BIAS_POWERSAVE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + PowerSave VDD Voltage Bias - % of bias (signed twos complement in 0.5 + percent steps) that is applied to the UltraTurbo VPD point used in + calculating the Global Pstate values. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + </description> + <valueType>int8</valueType> + <platInit/> + <initToZero/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VCS_BIAS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + VCS Voltage Bias - % of bias (signed twos complement in 0.5 percent + steps) that is applied to the VCS value stored in the UltraTurbo VPD + point for setting the VCS rail. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_EXT_VDN_BIAS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + VDN Voltage Bias - % of bias (signed twos complement in 0.5 percent + steps) that is applied to the VDN value stored in the VPD for setting the + VDN rail. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_INT_VDD_BIAS_ULTRATURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS + WELL AS THE IVRM VOLTAGE CALCULATION PROCESS + UltraTurbo Internal VDD Voltage Bias - % of bias (signed twos complement in + 0.5 percent steps) that is applied to the voltage computed (Vout) as part + of the Local Pstate. Note: the Vin Effective that models the Vin to the + PFETs (i.e accounting for system parameter losses) may include biassing + based on ATTR_VOLTAGE_VDD_BIAS_ULTRATURBO. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_INT_VDD_BIAS_TURBO</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS + WELL AS THE IVRM VOLTAGE CALCULATION PROCESS + TURBO Internal VDD Voltage Bias - % of bias (signed twos complement in 0.5 + percent steps) that is applied to the voltage computed (Vout) as part of + the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs + (i.e accounting for system parameter losses) may include biassing based on + ATTR_VOLTAGE_VDD_BIAS_TURBO. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_INT_VDD_BIAS_NOMINAL</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS + WELL AS THE IVRM VOLTAGE CALCULATION PROCESS + Nominal Internal VDD Voltage Bias - % of bias (signed twos complement in + 0.5 percent steps) that is applied to the voltage computed (Vout) as part + of the Local Pstate. Note: the Vin Effective that models the Vin to the + PFETs (i.e accounting for system parameter losses) may include biassing + based on ATTR_VOLTAGE_VDD_BIAS_NOMINAL. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VOLTAGE_INT_VDD_BIAS_POWERSAVE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + TODO (RTC 136996) NEED TO LOOK AT PERCENTAGE IMPLEMENTATION IN CME CODE AS + WELL AS THE IVRM VOLTAGE CALCULATION PROCESS + PowerSave Internal VDD Voltage Bias - % of bias (signed twos complement in + 0.5 percent steps) that is applied to the voltage computed (Vout) as part of + the Local Pstate. Note: the Vin Effective that models the Vin to the PFETs + (i.e accounting for system parameter losses) may include biassing based on + ATTR_VOLTAGE_VDD_BIAS_POWERSAVE. + + Producer: Attribute Overrides by Lab/Mfg Characterization Team + + Consumer: p9_pstate_parameter_block + + Platform default: 0 + </description> + <valueType>int8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_STOP4_DISABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Control CME response to execution of PowerPC STOP instruction + + if OFF, treat STOP4 as STOP4 + if ON, treat STOP4 as STOP2 + + Producer: ??? + + Consumer: p8_hcode_image_build.C + + Platform default: OFF + </description> + <valueType>uint8</valueType> + <enum>OFF=0, ON=1</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_STOP8_DISABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Control CME response to execution of PowerPC STOP instruction + + if OFF, treat STOP8 as STOP8 + if ON, treat STOP8 as STOP4 + + Producer: ??? + + Consumer: p8_hcode_image_build.C + + Platform default: OFF + </description> + <valueType>uint8</valueType> + <enum>OFF=0, ON=1</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_STOP11_DISABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Control CME response to execution of PowerPC STOP instruction + + if OFF, treat STOP11 as STOP11 + if ON, treat STOP11 as STOP8 + + Producer: ??? + + Consumer: p8_hcode_image_build.C + + Platform default: OFF + </description> + <valueType>uint8</valueType> + <enum>OFF=0, ON=1</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_IVRMS_ENABLED</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>System control to allow (if all other attribute tests yield + true values) or categorically disallow IVRM enablement + + Producer: MRWB + + Consumers: p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE/OCC + CME Quad Pstate Region (CQPR) for CM Quad Manager + + Platform default: FALSE + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_WOF_ENABLED</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>System control to allow Work Load Optimized Frequency (WOF) + algorithms to modify frequency based on active core count and other inputs. + + Producer: MRWB + + Consumers: p9_build_pstate_datablock -> + Pstate Parameter Block (PSPB) for PGPE/OCC + + Platform default: FALSE + </description> + <valueType>uint8</valueType> + <enum>FALSE=0, TRUE=1</enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PFET_POWERUP_DELAY_NS</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Time (in nanoseconds) between PFET controller steps (7 of them) when turning + the PFETS ON + + Producer: MRWB + + Consumers: p9_pm_pfet_init + + Platform default: + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PFET_POWERDOWN_DELAY_NS</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Time (in nanoseconds) between PFET controller steps (7 of them) when turning + the PFETS OFF + + Producer: MRWB + + Consumers: p9_pm_pfet_init + + Platform default: + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PFET_VDD_VOFF_SEL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Selection of the OFF setting for the core and cache chiplet VDD PFET controllers + + Producer: MRWB + + Consumers: p9_pm_pfet_init + + Platform default: + </description> + <valueType>uint8</valueType> + <enum> + NOOFF = 0x00, + ALLBUT1TO7OFF = 0x01, + ALLBUT2TO7OFF = 0x02, + ALLBUT3TO7OFF = 0x03, + ALLBUT4TO7OFF = 0x04, + ALLBUT5TO7OFF = 0x05, + ALLBUT6TO7OFF = 0x06, + ALLBUT7OFF = 0x7, + ALLOFF = 0x08 + </enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PFET_VCS_VOFF_SEL</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Selection of the OFF setting for the core and cache chiplet VCS PFET + controllers + + Producer: MRWB + + Consumers: p9_pm_pfet_init + + Platform default: + </description> + <valueType>uint8</valueType> + <enum> + NOOFF = 0x00, + ALLBUT1TO7OFF = 0x01, + ALLBUT2TO7OFF = 0x02, + ALLBUT3TO7OFF = 0x03, + ALLBUT4TO7OFF = 0x04, + ALLBUT5TO7OFF = 0x05, + ALLBUT6TO7OFF = 0x06, + ALLBUT7OFF = 0x7, + ALLOFF = 0x08 + </enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PBAX_GROUPID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Receive PBAX Groupid. Value that indicates this PBA's PBAX Group affinity. + This is matched to pbax_groupid of the PMISC Address phase. + + Provided by the Machine Readable Workbook. + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PBAX_CHIPID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Receive PBAX Chipid. Value that indicates this PBA's PBAX Chipid within + the PBAX node. Is matched to pbax_chipid of the Address phase if + pbax_type=unicast. + + Provided by the Machine Readable Workbook. + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_PBAX_BRDCST_ID_VECTOR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Receive PBAX Broadcast Group. Vector that is indexed when decoded PMISC + pbax_type=broadcast with the decoded PMISC pbax_chipid value. If the + bit in this vector at the decoded bit location is a 1, then this receive + engine will participate in the broadcast operation. + + Provided by the Machine Readable Workbook. + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_POUNDV_BUCKET_NUM_OVERRIDE</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description> + 1 if override of poundv bucket num is available. + 0 if override is unavailable. + </description> + <initToZero/> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_POUNDV_BUCKET_NUM</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description> + Attribute in place to allow override of which POUNDV + bucket to use to set power management data. + 1 = Bucket A + 2 = Bucket B + 3 = Bucket C + 4 = Bucket D + 5 = Bucket E + 6 = Bucket F + </description> + <initToZero/> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_POUNDV_BUCKET_DATA</id> + <targetType>TARGET_TYPE_EQ</targetType> + <description> + Power Management data for Quad targets. Stored as an array of bytes. + The data is read directly from VPD and stored in this attribute without + being altered. + + NOTE: you may need to handle correcting endiannessif you are using this + attribute. + </description> + <valueType>uint8</valueType> + <initToZero/> + <array>61</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DUMP_STOP_INFO_SUPPRESS_ERROR_TRACE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + if set to 1, FAPI_ERR records are suppressed from being produced by + p9_dump_stop_info. + </description> + <valueType>uint8</valueType> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DUMP_STOP_INFO_ENABLE_ERRORLOG</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + if set to 1, p9_dump_stop_info output will be written to error logs + </description> + <valueType>uint8</valueType> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Controls the enablement of Voltage Droop Monitors (VDM) in the system. + + Producer: Machine Readable Workbook + + Consumers: + p9_pstate_parameter_block to set flag for CME QuadManager Hcode + reaction + p9_hcd_cache procedures to power on VDMs before CME booting + </description> + <valueType>uint8</valueType> + <enum>OFF = 0x00, ON = 0x01</enum> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_DROOP_SMALL_OVERRIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Voltage Droop Monitor (VDM) Small Threshold Select Value per VPD point + The enum indicates a negative value below the VDM setting that will + trigger a small droop event. + + Array of 5 entries: + 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable + + If index 4 is non-zero, the other entries are considered valid. + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x00, + 8mV = 0x01, + 16mV = 0x02, + 24mV = 0x03, + 32mV = 0x04, + 40mV = 0x05, + 48mV = 0x06, + 56mV = 0x07, + 64mV = 0x08, + 72mV = 0x09, + 80mV = 0x0A, + 88mV = 0x0B, + 92mV = 0x0C, + 96mV = 0x0D + </enum> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_DROOP_LARGE_OVERRIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Voltage Droop Monitor (VDM) Large Threshold Select Value per VPD point + The enum indicates a negative value below the VDM setting that will + trigger a large droop event. + + Array of 5 entries: + 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable + + If index 4 is non-zero, the other entries are considered valid. + + Producer: Firmware override + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x00, + 8mV = 0x01, + 16mV = 0x02, + 24mV = 0x03, + 32mV = 0x04, + 40mV = 0x05, + 48mV = 0x06, + 56mV = 0x07, + 64mV = 0x08, + 72mV = 0x09, + 80mV = 0x0A, + 88mV = 0x0B, + 92mV = 0x0C, + 96mV = 0x0D + </enum> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_DROOP_EXTREME_OVERRIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Voltage Droop Monitor (VDM) Extreme Threshold Select Value per VPD point. + The enum indicates a negative value below the VDM setting that will + trigger an extreme droop event. + + Array of 5 entries: + 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable + + If index 4 is non-zero, the other entries are considered valid. + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x00, + 8mV = 0x01, + 16mV = 0x02, + 24mV = 0x03, + 32mV = 0x04, + 40mV = 0x05, + 48mV = 0x06, + 56mV = 0x07, + 64mV = 0x08, + 72mV = 0x09, + 80mV = 0x0A, + 88mV = 0x0B, + 92mV = 0x0C, + 96mV = 0x0D + </enum> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_OVERVOLT_OVERRIDE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Voltage Droop Monitor (VDM) OverVoltage Threshold Select Value per VPD + point. The enum indicates a positive value above the VDM setting that will + indicate an overvolt droop condition. + + Array of 5 entries: + 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable + + If index 4 is non-zero, the other entries are considered valid. + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <enum> + FORCE = 0x00, + 8mV = 0x01, + 16mV = 0x02, + 24mV = 0x03, + 32mV = 0x04, + 40mV = 0x05, + 48mV = 0x06, + 56mV = 0x07, + 64mV = 0x08 + </enum> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_FMAX_OVERRIDE_KHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + + Producer: MRWB. + </description> + <valueType>uint16</valueType> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_FMIN_OVERRIDE_KHZ</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + + + Producer: MRWB. + </description> + <valueType>uint16</valueType> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_VDM_VID_COMPARE_OVERRIDE_MV</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Voltage Droop Monitor (VDM) Voltage Compare Voltage to expect when no + droop is present (binary in mV) + + Array of 5 entries: + 0 = PowerSave, 1 = Nominal; 2 = Turbo; 3 = UltraTurbo; 4 = Enable + + If index 4 is non-zero, the other entries are considered valid. + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <array>5</array> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DPLL_DYNAMIC_FMAX_ENABLE</id> + <description> + Allow increased dynamic frequency in response to excess voltage margin + Controlled by VDM_OVERVOLT threshold value in VDM Configuration Register. + + Producer: MRWB. + </description> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <valueType>uint8</valueType> + <enum> + OFF = 0x00,ON = 0x01 + </enum> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DPLL_DYNAMIC_FMIN_ENABLE</id> + <description> + Allow decreased dynamic frequency in response to loss of voltage margin. + Controlled by VDM_DROOP_SMALL threshold value in VDM Configuration + Register. + + Producer: MRWB. + </description> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <valueType>uint8</valueType> + <enum> + OFF = 0x00,ON = 0x01 + </enum> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DPLL_DROOP_PROTECT_ENABLE</id> + <description> + Enable instantaneous frequency reduction in response to droop events + Controlled by VDM_DROOP_SMALL, _LARGE and _XTREME threshold values in VDM + Configuration Register. The amount of reduction is controlled by chip + initialization values + + Producer: MRWB. + </description> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <valueType>uint8</valueType> + <enum> + OFF = 0x00,ON = 0x01 + </enum> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_DPLL_VDM_RESPONSE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Indicates the response of the DPLL frequency upon VDM events. This + control will only apply if ATTR_DPLL_VDM_JUMP_ENABLE is ON; + Hardware WOF = DROOP_PROTECT_OVERVOLT (slew to Fmax if margin exists) + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <enum> + STATIC_FREQ = 0x00, + STATIC_DROOP_PROTECT = 0x01, + DROOP_PROTECT_OVERVOLT = 0x02, + DYNAMIC_FREQ = 0x04 + </enum> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_IVRM_DEADZONE_MV</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Indicates the size of the deadzone where the iVRM cannot regulate + (binary in millivolts) + + Producer: MRWB. + </description> + <valueType>uint8</valueType> + <initToZero/> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_TDP_RDP_CURRENT_FACTOR</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> TODO RTC 157943 -- Placeholder description + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint32</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_STEP_DELAY</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Minimum delay (in nanoseconds) between clock grid management transition + steps + + Producer: MRWB + + Consumers: p9_build_pstate_datablock -> + CME Quad Pstate Region (CQPR) for CM Quad Manager + + Platform default: 0 + </description> + <valueType>uint8</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_FREQ_REGIONS</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Frequency discontinuity region points that defines the lower edge of a + Resonant Region and where F[i] LT F[i+1] and 0 LE i LE 7. + This yields: + ATTR_RESCLK_FREQ_REGIONS[0] LE Region 0 LT ATTR_RESCLK_FREQ_REGIONS[1] + ATTR_RESCLK_FREQ_REGIONS[1] LE Region 1 LT ATTR_RESCLK_FREQ_REGIONS[2] + ATTR_RESCLK_FREQ_REGIONS[2] LE Region 2 LT ATTR_RESCLK_FREQ_REGIONS[3] + etc. + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint8</valueType> + <array>8</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_FREQ_REGION_INDEX</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Defines the index into ATTR_RESCLK_VALUE[] to use for the frequency region. + + The frequency associated with the region is defined by + ATTR_RESCLK_FREQ_REGIONS[i] and ATTR_RESCLK_FREQ_REGIONS[i+1] for + 0 LE i LE 7. + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint8</valueType> + <array>8</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_VALUE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Array of Clock strength values that will we written in QACCR by CME Hcode + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint16</valueType> + <array>64</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_L3_VALUE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Array of L3 Clock strength values to be used going between "High and Normal + Voltage" and "Low Voltage" mode. Low Voltage mode is define by + ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV. + + Entry 0 = "High and Normal Voltage" setting + Entry 3 = "High and Normal Voltage" setting + + Entry 1 = transitional setting defined by the clock team + Entry 2 = transitional setting defined by the clock team + + Contents of each entry will be written directly into L3 control bits in the + QACCR(16:23) a RMW operations. If the circuits demand a grey code whereby + only 1 bit of this field can change at a time, the entries must be deal with + such encoding. The Hcode that these values does not perform that function; + it merely steps from 0->3 when going below the voltage defined by + ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV and then steps 3->0 when going at or + above the voltage defined by ATTR_RESCLK_L3_VOLTAGE_THRESHOLD_MV. + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint8</valueType> + <array>4</array> + <platInit/> + </attribute> + <!-- ********************************************************************* --> + <attribute> + <id>ATTR_SYSTEM_RESCLK_L3_VOLTAGE_THRESHOLD_MV</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Voltage value (in millivolts) whereby voltage below this value will have + the L3 clock strength moved to "Low" mode while values at or above this + value will have the L3 clock strength moved to "High" mode. The L3 clock + strength values put in the hardware for this mode transtion are defined by + ATTR_RESCLK_L3_VALUE. + + Consumers: p9_pstate_parameter_block + </description> + <valueType>uint16</valueType> + <platInit/> + </attribute> + <!-- ********************************************************************* --> +</attributes> |
