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-rw-r--r--src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml44
1 files changed, 30 insertions, 14 deletions
diff --git a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
index 450f286c..5b0c6563 100644
--- a/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
+++ b/src/import/chips/p9/procedures/xml/attribute_info/memory_mcs_attributes.xml
@@ -1930,22 +1930,38 @@
<id>ATTR_MSS_CAL_STEP_ENABLE</id>
<targetType>TARGET_TYPE_MCS</targetType>
<description>
- A bit map of vector denoting valid cal steps to run (0 is left most bit)
- [0] EXT_ZQCAL
- [1] WR_LEVEL
- [2] DQS_ALIGN
- [3] RDCLK_ALIGN
- [4] READ_CTR
- [5] READ_CTR_2D_VREF
- [6] WRITE_CTR
- [7] WRITE_CTR_2D_VREF
- [8] COARSE_WR
- [9] COARSE_RD
- [10]:[15] Reserved for future use
- COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL.
+ A bit map of vector denoting valid steps to run (0 is left most bit)
+ [0] DRAM_ZQCAL
+ [1] DB_ZQCAL (LRDIMM)
+ [2] MREP (LRDIMM)
+ [3] MRD - Coarse (LRDIMM)
+ [4] MRD - Fine (LRDIMM)
+ [5] WR_LEVEL
+ [6] INITIAL_PAT_WR
+ [7] WR_VREF_LATCH
+ [8] DWL (LRDIMM)
+ [9] MWD - Coarse (LRDIMM)
+ [10] MWD - Fine (LRDIMM)
+ [11] HWL (LRDIMM)
+ [12] DQS_ALIGN
+ [13] RDCLK_ALIGN
+ [14] READ_CTR_2D_VREF
+ [15] READ_CTR
+ [16] WRITE_CTR_2D_VREF
+ [17] WRITE_CTR
+ [18] COARSE_WR
+ [19] COARSE_RD
+ [20]:[31] Reserved for future use
+
+ COARSE_WR and COARSE_RD will be consumed together to form COARSE_LVL.
+
+ WRITE_CTR will be run, even if only WRITE_CTR_2D_VREF is enabled,
+ as the WR 2D VREF HW cal depends upon WRITE_CTR 1D to function.
+
+ Note: LRDIMM steps will only be enabled for LRDIMMs and won't run on RDIMMs.
</description>
<initToZero></initToZero>
- <valueType>uint16</valueType>
+ <valueType>uint32</valueType>
<writeable/>
<array>2</array>
<mssAccessorName>cal_step_enable</mssAccessorName>
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