diff options
Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C')
-rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C | 128 |
1 files changed, 102 insertions, 26 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C index 0e24508f..115b19c5 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_tp_chiplet_init1.C @@ -5,7 +5,7 @@ /* */ /* OpenPOWER sbe Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015,2017 */ +/* Contributors Listed Below - COPYRIGHT 2015,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -42,12 +42,16 @@ #include <p9_perv_scom_addresses_fld.H> #include <p9n2_perv_scom_addresses_fld.H> #include <p9_perv_sbe_cmn.H> - +#include <p9_sbe_common.H> enum P9_SBE_TP_CHIPLET_INIT1_Private_Constants { + START_CMD = 0x1, + CLOCK_TYPES_ALL = 0x7, + REGIONS_PIB_NET = 0x300, SCAN_TYPES_EXCEPT_TIME_GPTR_REPR = 0xDCF, REGIONS_EXCEPT_VITAL_PIB_NET = 0x4FF, // Regions excluding VITAL, PIB and NET + REGIONS_EXCEPT_VITAL_PIB_NET_SBE = 0x4DF, // Regions excluding VITAL, PIB, NET and SBE SCAN_TYPES_TIME_GPTR_REPR = 0x230 }; @@ -58,7 +62,18 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const fapi2::buffer<uint64_t> l_data64; fapi2::buffer<uint64_t> l_data64_perv_ctrl0; fapi2::buffer<uint64_t> l_data64_root_ctrl0; + fapi2::buffer<uint64_t> l_data64_cplt_ctrl1; + fapi2::buffer<uint64_t> l_read_reg; fapi2::buffer<uint8_t> l_read_attr; +#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__) + fapi2::buffer<uint8_t> l_is_axone; +#endif + fapi2::buffer<uint64_t> l_clk_regions; +#ifndef __PPE__ + fapi2::Target<fapi2::TARGET_TYPE_PERV> l_tpchiplet = + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0]; +#endif FAPI_INF("p9_sbe_tp_chiplet_init1: Entering ..."); FAPI_DBG("Disable local clock gating VITAL"); @@ -66,6 +81,10 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const i_target_chip, l_read_attr)); FAPI_DBG("l_read_attr is %d", l_read_attr); +#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__) + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9A_SBE_REGION, i_target_chip, l_is_axone)); +#endif + //Getting PERV_CTRL0 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); @@ -81,24 +100,66 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const l_data64_perv_ctrl0)); } - FAPI_DBG("Release PCB Reset"); - //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 - l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0)); +#ifndef __PPE__ - FAPI_DBG("Enable PCB auto-reset"); - l_data64.flush<0>().setBit<PERV_RESET_REG_TIMEOUT_EN>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_RESET_REG, l_data64)); - - FAPI_DBG("Set Chiplet Enable"); - //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 - l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); - - FAPI_DBG("Drop TP Chiplet Fence Enable"); - //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 - l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + if(l_is_axone) + { + FAPI_DBG("Release PCB Reset"); + //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 + l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0)); + + FAPI_DBG("Set Chiplet Enable"); + //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 + l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + + FAPI_DBG("Drop TP Chiplet Fence Enable"); + //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + + FAPI_DBG("Drop NET and PIB region fence") + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_CPLT_CTRL1, l_data64_cplt_ctrl1)); + l_data64_cplt_ctrl1.clearBit<PERV_1_CPLT_CTRL1_UNUSED_5B>(); + l_data64_cplt_ctrl1.clearBit<PERV_1_CPLT_CTRL1_UNUSED_6B>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_CPLT_CTRL1, l_data64_cplt_ctrl1)); + + FAPI_DBG("Starting clock for PIB and NET"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_64(l_tpchiplet, REGIONS_PIB_NET, l_clk_regions)); + FAPI_DBG("l_clk_regions value: %#018lX", l_clk_regions); + FAPI_TRY(p9_sbe_common_clock_start_stop(l_tpchiplet, START_CMD, 0, 0, l_clk_regions, CLOCK_TYPES_ALL)); + + FAPI_DBG("Switching to PCB2PCB path") + FAPI_TRY(p9_perv_sbe_cmn_switch_to_pcb2pcb_path_scom( + i_target_chip)); + + //Getting ROOT_CTRL0 register value again as it is changed in above function + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, + l_data64_root_ctrl0)); + } + else +#endif + { + FAPI_DBG("Release PCB Reset"); + //PIB.ROOT_CTRL0.PCB_RESET_DC = 0 + l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_PCB_RESET_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0)); + + FAPI_DBG("Enable PCB auto-reset"); + l_data64.flush<0>().setBit<PERV_RESET_REG_TIMEOUT_EN>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_RESET_REG, l_data64)); + + FAPI_DBG("Set Chiplet Enable"); + //PIB.PERV_CTRL0.TP_CHIPLET_EN_DC = 1 + l_data64_perv_ctrl0.setBit<PERV_PERV_CTRL0_SET_TP_CHIPLET_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + + FAPI_DBG("Drop TP Chiplet Fence Enable"); + //PIB.PERV_CTRL0.TP_FENCE_EN_DC = 0 + l_data64_perv_ctrl0.clearBit<PERV_PERV_CTRL0_SET_TP_FENCE_EN_DC>(); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_PERV_CTRL0_SCOM, l_data64_perv_ctrl0)); + } FAPI_DBG("Drop Global Endpoint reset"); //PIB.ROOT_CTRL0.GLOBAL_EP_RESET_DC = 0 @@ -110,18 +171,33 @@ fapi2::ReturnCode p9_sbe_tp_chiplet_init1(const l_data64_root_ctrl0.clearBit<PERV_ROOT_CTRL0_SET_OOB_MUX>(); //PIB.ROOT_CTRL0.OOB_MUX = 0 FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ROOT_CTRL0_SCOM, l_data64_root_ctrl0)); - FAPI_DBG("Region setup call"); - FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( - i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, - fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions)); - FAPI_DBG("l_regions value : %#018lX", l_regions); +#if defined(SBE_AXONE_CONFIG) || !defined(__PPE__) + + if(l_is_axone) + { + + FAPI_DBG("Region setup call"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET_SBE, l_regions)); + FAPI_DBG("l_regions value : %#018lX", l_regions); + } + else +#endif + { + FAPI_DBG("Region setup call"); + FAPI_TRY(p9_perv_sbe_cmn_regions_setup_16( + i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, + fapi2::TARGET_STATE_FUNCTIONAL)[0], REGIONS_EXCEPT_VITAL_PIB_NET, l_regions)); + FAPI_DBG("l_regions value : %#018lX", l_regions); + } - FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types GPTR, TIME, REPR"); + FAPI_DBG("Run scan0 module for region except vital,PIB,NET,SBE(SBE only for axone), scan types GPTR, TIME, REPR"); FAPI_TRY(p9_perv_sbe_cmn_scan0_module( i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, SCAN_TYPES_TIME_GPTR_REPR)); - FAPI_DBG("run scan0 module for region except vital,PIB,net, scan types except GPTR, TIME, REPR"); + FAPI_DBG("Run scan0 module for region except vital,PIB,NET,SBE(SBE only for axone), scan types except GPTR, TIME, REPR"); FAPI_TRY(p9_perv_sbe_cmn_scan0_module( i_target_chip.getChildren<fapi2::TARGET_TYPE_PERV>(fapi2::TARGET_FILTER_TP, fapi2::TARGET_STATE_FUNCTIONAL)[0], l_regions, |