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Diffstat (limited to 'src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C')
-rw-r--r--src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
index fac39832..9b8cddd4 100644
--- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
+++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C
@@ -215,6 +215,16 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const
for (auto& targ : l_perv_func_WO_Core_Cache)
{
FAPI_DBG("Configuring multicasting registers for Mc,Nest,Xb,Obus,pcie chiplets");
+
+ // if in ASYNC mode DO NOT add to multicast groups because the chiplet is non
+ // responsive. Wait until clocks are started up in hostboot
+ uint32_t l_chipletID = targ.getChipletNumber();
+
+ if((l_chipletID >= 7 && l_chipletID <= 8) && (!l_mc_sync_mode))
+ {
+ continue;
+ }
+
FAPI_TRY(p9_sbe_chiplet_reset_mc_setup(targ));
}
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