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-rwxr-xr-xsbe/test/testGetCapabilities.py2
-rw-r--r--sbe/test/testGetMem.py51
-rw-r--r--sbe/test/testGetMem_expdata.py60
-rw-r--r--sbe/test/testPutGetMem.xml26
-rw-r--r--sbe/test/testPutMem.py60
-rw-r--r--sbe/test/testPutMem_fail.py61
6 files changed, 259 insertions, 1 deletions
diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py
index 4b631270..8fa9d241 100755
--- a/sbe/test/testGetCapabilities.py
+++ b/sbe/test/testGetCapabilities.py
@@ -15,7 +15,7 @@ EXPDATA1 = [0x0,0x0,0x0,0x0,
0x0,0x0,0x0,0x0,
0x00,0x0,0x0,0x0];
-EXPDATA2 = [0x0,0x0,0x0,0x0,
+EXPDATA2 = [0xa4,0x0,0x0,0x03,
0x0,0x0,0x0,0x0,
0x0,0x0,0x0,0x0,
0x0,0x0,0x0,0x0,
diff --git a/sbe/test/testGetMem.py b/sbe/test/testGetMem.py
new file mode 100644
index 00000000..dac6b747
--- /dev/null
+++ b/sbe/test/testGetMem.py
@@ -0,0 +1,51 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 1
+
+GETMEM_TESTDATA = [0,0,0,0x6,
+ 0,0,0xA4,0x01,
+ 0,0,0x0,0x02,
+ 0,0,0,0,
+ 0x08,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x80] # length of data
+
+GETMEM_EXPDATA = [0x00,0x00,0x00,0x80, # length of data
+ 0xc0,0xde,0xa4,0x01,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x03];
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+
+ # GetMem test
+ testUtil.writeUsFifo( GETMEM_TESTDATA )
+ testUtil.writeEot( )
+ # GetMem chipOp would send the read data first,
+ # thus, would attempt to read the expected length of data first
+ loop = 1
+ while ( loop <= LOOP_COUNT ):
+ testUtil.readDsEntry ( 32 ) ## 32 entries ~ 128B PBA granule
+ loop += 1
+ testUtil.readDsFifo( GETMEM_EXPDATA )
+ testUtil.readEot( )
+
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
diff --git a/sbe/test/testGetMem_expdata.py b/sbe/test/testGetMem_expdata.py
new file mode 100644
index 00000000..78304c5a
--- /dev/null
+++ b/sbe/test/testGetMem_expdata.py
@@ -0,0 +1,60 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 4
+
+GETMEM_TESTDATA = [0,0,0,0x6,
+ 0,0,0xA4,0x01,
+ 0,0,0x0,0x02,
+ 0,0,0,0,
+ 0x08,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x80] # length of data
+
+GETMEM_EXP_RESPHDR = [0x00,0x00,0x00,0x80, # length of data
+ 0xc0,0xde,0xa4,0x01,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x03]
+
+GETMEM_EXP_RESPDATA = [0xAB,0xCD,0xEF,0x01,
+ 0xAB,0xCD,0xEF,0x02,
+ 0xAB,0xCD,0xEF,0x03,
+ 0xAB,0xCD,0xEF,0x04,
+ 0xAB,0xCD,0xEF,0x05,
+ 0xAB,0xCD,0xEF,0x06,
+ 0xAB,0xCD,0xEF,0x07,
+ 0xAB,0xCD,0xEF,0x08]
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+
+ # GetMem test
+ testUtil.writeUsFifo( GETMEM_TESTDATA )
+ testUtil.writeEot( )
+ # GetMem chipOp would send the read data first,
+ # thus, would attempt to read the expected length of data first
+ loop = 1
+ while ( loop <= LOOP_COUNT ):
+ testUtil.readDsFifo ( GETMEM_EXP_RESPDATA )
+ loop += 1
+ testUtil.readDsFifo( GETMEM_EXP_RESPHDR )
+ testUtil.readEot( )
+
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
diff --git a/sbe/test/testPutGetMem.xml b/sbe/test/testPutGetMem.xml
new file mode 100644
index 00000000..49212786
--- /dev/null
+++ b/sbe/test/testPutGetMem.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8"?>
+
+ <!-- Workaround to set clock regs. Once simics have fix, we can remove it -->
+ <testcase>
+ <simcmd>p9Proc0.proc_chip.invoke parallel_store LOGIC 0xffc50000 \"00000000_00000001\" 64</simcmd>
+ </testcase>
+ <!-- Workaround to configure L3 cache on Simics. Once simics have all the support integrated, we can remove it -->
+ <testcase>
+ <simcmd>p9Proc0.proc_fsi2host_mbox->responder_enable =1</simcmd>
+ <simcmd>@conf.p9Proc0.proc_chip.iface.signal.signal_raise()</simcmd>
+ <simcmd>p9Proc0.proc_chip.invoke parallel_store STARTSBEREGS 0 "80000000" 32</simcmd>
+ </testcase>
+ <!-- Run trace script framework -->
+ <testcase>
+ <simcmd>run-python-file simics-debug-framework.py</simcmd>
+ </testcase>
+ <!-- Write value to the PBA region and then read it back -->
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testPutMem.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetMem_expdata.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+
diff --git a/sbe/test/testPutMem.py b/sbe/test/testPutMem.py
new file mode 100644
index 00000000..8ba710bb
--- /dev/null
+++ b/sbe/test/testPutMem.py
@@ -0,0 +1,60 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 4
+
+PUTMEM_TEST_HDR = [0,0,0,0x86,
+ 0,0,0xA4,0x02,
+ 0,0,0x0,0x02,
+ 0,0,0,0,
+ 0x08,0x00,0x00,0x00,
+ 0x00,0x00,0x00,0x80]
+
+PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01,
+ 0xAB,0xCD,0xEF,0x02,
+ 0xAB,0xCD,0xEF,0x03,
+ 0xAB,0xCD,0xEF,0x04,
+ 0xAB,0xCD,0xEF,0x05,
+ 0xAB,0xCD,0xEF,0x06,
+ 0xAB,0xCD,0xEF,0x07,
+ 0xAB,0xCD,0xEF,0x08]
+
+PUTMEM_EXPDATA = [0x00,0x00,0x00,0x80,
+ 0xc0,0xde,0xa4,0x02,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x03]
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+
+ testUtil.writeUsFifo( PUTMEM_TEST_HDR )
+
+ loop = 1
+ while (loop <= LOOP_COUNT):
+ #testUtil.runCycles( 10000000 )
+ testUtil.writeUsFifo( PUTMEM_TEST_DATA )
+ loop += 1
+ testUtil.writeEot( )
+
+ #testUtil.runCycles( 10000000 )
+ testUtil.readDsFifo( PUTMEM_EXPDATA )
+ testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
diff --git a/sbe/test/testPutMem_fail.py b/sbe/test/testPutMem_fail.py
new file mode 100644
index 00000000..8e6c4cc4
--- /dev/null
+++ b/sbe/test/testPutMem_fail.py
@@ -0,0 +1,61 @@
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 4
+
+PUTMEM_TEST_HDR = [0,0,0x00,0x86,
+ 0,0,0xA4,0x02,
+ 0,0,0x0,0x02,
+ 0,0,0,0,
+ 0x08,0x00,0x00,0x04, # Un-aligned PBA Address
+ 0x00,0x00,0x00,0x80]
+
+PUTMEM_TEST_DATA = [0xAB,0xCD,0xEF,0x01,
+ 0xAB,0xCD,0xEF,0x02,
+ 0xAB,0xCD,0xEF,0x03,
+ 0xAB,0xCD,0xEF,0x04,
+ 0xAB,0xCD,0xEF,0x05,
+ 0xAB,0xCD,0xEF,0x06,
+ 0xAB,0xCD,0xEF,0x07,
+ 0xAB,0xCD,0xEF,0x08]
+
+PUTMEM_EXPDATA = [0x00,0x00,0x00,0x00,
+ 0xc0,0xde,0xa4,0x02,
+ 0x00,0xfe,0x00,0x0a,
+ 0xff,0xdc,0x00,0x03,
+ 0x00,0x00,0x00,0x00,
+ 0x00,0xf8,0x82,0x19,
+ 0x00,0x00,0x00,0x06]
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+
+ testUtil.writeUsFifo( PUTMEM_TEST_HDR )
+
+ loop = 1
+ while (loop <= LOOP_COUNT):
+ testUtil.writeUsFifo( PUTMEM_TEST_DATA )
+ loop += 1
+ testUtil.writeEot( )
+
+ testUtil.readDsFifo( PUTMEM_EXPDATA )
+ testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
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