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-rwxr-xr-xsbe/test/test.xml2
-rwxr-xr-xsbe/test/testGetCapabilities.py26
-rw-r--r--sbe/test/testGetRing.py96
-rwxr-xr-xsbe/test/testGetRing.xml30
4 files changed, 153 insertions, 1 deletions
diff --git a/sbe/test/test.xml b/sbe/test/test.xml
index 2564be1d..b06da370 100755
--- a/sbe/test/test.xml
+++ b/sbe/test/test.xml
@@ -22,6 +22,7 @@
<!-- permissions and limitations under the License. -->
<!-- -->
<!-- IBM_PROLOG_END_TAG -->
+
<integrationtest>
<platform startsimargs="--notar --norun --sim_parms -nre">
<machine>%%machine%%</machine>
@@ -39,6 +40,7 @@
<include>../simics/targets/p9_nimbus/sbeTest/testFifoReset.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testAduMem.xml</include>
<include>../simics/targets/p9_nimbus/sbeTest/testExecutorPutRing.xml</include>
+ <include>../simics/targets/p9_nimbus/sbeTest/testGetRing.xml</include>
<testcase>
<simcmd>sbe-trace 0</simcmd>
</testcase>
diff --git a/sbe/test/testGetCapabilities.py b/sbe/test/testGetCapabilities.py
index f9292532..a9287558 100755
--- a/sbe/test/testGetCapabilities.py
+++ b/sbe/test/testGetCapabilities.py
@@ -1,3 +1,27 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: sbe/test/testGetCapabilities.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2015,2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
import sys
sys.path.append("targets/p9_nimbus/sbeTest" )
import testUtil
@@ -12,7 +36,7 @@ EXPDATA1 = [0x0,0x0,0x0,0x0,
0x0,0x0,0x0,0x0,
0xa2,0x0,0x0,0x0f, #getscom/putscom/modifyscom/putscomundermask
0x0,0x0,0x0,0x0,
- 0x0,0x0,0x0,0x0,
+ 0xa3,0x0,0x0,0x1, #getring
0x00,0x0,0x0,0x0];
EXPDATA2 = [0xa4,0x0,0x0,0x0f, #GetMemPba/PutMemPba/GetSramOcc/PutSramOcc
diff --git a/sbe/test/testGetRing.py b/sbe/test/testGetRing.py
new file mode 100644
index 00000000..4137108d
--- /dev/null
+++ b/sbe/test/testGetRing.py
@@ -0,0 +1,96 @@
+# IBM_PROLOG_BEGIN_TAG
+# This is an automatically generated prolog.
+#
+# $Source: sbe/test/testGetRing.py $
+#
+# OpenPOWER sbe Project
+#
+# Contributors Listed Below - COPYRIGHT 2016
+# [+] International Business Machines Corp.
+#
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
+# implied. See the License for the specific language governing
+# permissions and limitations under the License.
+#
+# IBM_PROLOG_END_TAG
+import sys
+sys.path.append("targets/p9_nimbus/sbeTest" )
+import testUtil
+err = False
+#from testWrite import *
+
+LOOP_COUNT = 1
+
+#aligned Data
+GETRING_TESTDATA = [0,0,0,0x6,
+ 0,0,0xA3,0x01,
+ 0xa,0xa,0xa,0xa, # address
+ 0,0,0,0x40, # length of data
+ 0x00,0x00,0x00,0x01]
+
+GETRING_EXPDATA = [0,0,0,0, #data
+ 0,0,0,0, #data
+ 0,0,0,0x40, # length of data
+ 0xc0,0xde,0xa3,0x01,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x03];
+
+#Un-aligned Data
+GETRING_TESTDATA1 = [0,0,0,0x6,
+ 0,0,0xA3,0x01,
+ 0xa,0xa,0xa,0xa, # address
+ 0,0,0,0x45, # length of data
+ 0x00,0x00,0x00,0x01]
+
+GETRING_EXPDATA1 = [0,0,0,0, #data
+ 0,0,0,0, #data
+ 0,0,0,0, #data
+ 0,0,0,0, #data
+ 0,0,0,0x45, # length of data
+ 0xc0,0xde,0xa3,0x01,
+ 0x0,0x0,0x0,0x0,
+ 0x00,0x0,0x0,0x03];
+
+
+
+# MAIN Test Run Starts Here...
+#-------------------------------------------------
+def main( ):
+ testUtil.runCycles( 10000000 )
+
+ # GetRing test - Aligned Data
+ testUtil.writeUsFifo( GETRING_TESTDATA )
+ testUtil.writeEot( )
+ testUtil.readDsFifo( GETRING_EXPDATA )
+ testUtil.runCycles( 10000000 )
+ testUtil.readEot( )
+
+ # GetRing test - un-aligned Data
+ testUtil.runCycles( 10000000 )
+ testUtil.writeUsFifo( GETRING_TESTDATA1 )
+ testUtil.writeEot( )
+ testUtil.readDsFifo( GETRING_EXPDATA1 )
+ testUtil.runCycles( 10000000 )
+ testUtil.readEot( )
+
+#-------------------------------------------------
+# Calling all test code
+#-------------------------------------------------
+main()
+
+if err:
+ print ("\nTest Suite completed with error(s)")
+ #sys.exit(1)
+else:
+ print ("\nTest Suite completed with no errors")
+ #sys.exit(0);
+
diff --git a/sbe/test/testGetRing.xml b/sbe/test/testGetRing.xml
new file mode 100755
index 00000000..e3f240c1
--- /dev/null
+++ b/sbe/test/testGetRing.xml
@@ -0,0 +1,30 @@
+<!-- IBM_PROLOG_BEGIN_TAG -->
+<!-- This is an automatically generated prolog. -->
+<!-- -->
+<!-- $Source: sbe/test/testGetRing.xml $ -->
+<!-- -->
+<!-- OpenPOWER sbe Project -->
+<!-- -->
+<!-- Contributors Listed Below - COPYRIGHT 2016 -->
+<!-- [+] International Business Machines Corp. -->
+<!-- -->
+<!-- -->
+<!-- Licensed under the Apache License, Version 2.0 (the "License"); -->
+<!-- you may not use this file except in compliance with the License. -->
+<!-- You may obtain a copy of the License at -->
+<!-- -->
+<!-- http://www.apache.org/licenses/LICENSE-2.0 -->
+<!-- -->
+<!-- Unless required by applicable law or agreed to in writing, software -->
+<!-- distributed under the License is distributed on an "AS IS" BASIS, -->
+<!-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or -->
+<!-- implied. See the License for the specific language governing -->
+<!-- permissions and limitations under the License. -->
+<!-- -->
+<!-- IBM_PROLOG_END_TAG -->
+
+ <testcase>
+ <simcmd>run-python-file targets/p9_nimbus/sbeTest/testGetRing.py</simcmd>
+ <exitonerror>yes</exitonerror>
+ </testcase>
+
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