2 files changed, 37 insertions, 0 deletions
diff --git a/import/chips/p9/procedures/ppe/pk/std/std_common.h b/import/chips/p9/procedures/ppe/pk/std/std_common.h
index 358be9f1..a1f52eda 100644
--- a/import/chips/p9/procedures/ppe/pk/std/std_common.h
+++ b/import/chips/p9/procedures/ppe/pk/std/std_common.h
@@ -54,9 +54,19 @@
 /// 
 /// r1, r2, r3, and r13 must not be modified.  All other registers may be used.
 ///
+/// The pk_unified_irq_prty_mask_handler routine MUST return the task priority
+/// interrupt vector in d5.
+///
     .macro hwmacro_get_ext_irq
 
+#ifdef UNIFIED_IRQ_HANDLER_CME
+        // Unified approach.
+        _liw        r5, pk_unified_irq_prty_mask_handler
+        mtlr        r5
+        blrl            // On return, d5 contains task prty irq vec.
+#else
         _lvdg       d5, STD_LCL_EISTR    #load the 64bit interrupt status into d5
+#endif        
         cntlzw      r4, r5
         cmpwible    r4, 31, call_external_irq_handler   #branch if irq is lt or eq to 31
 
diff --git a/import/chips/p9/procedures/ppe/pk/std/std_irq.h b/import/chips/p9/procedures/ppe/pk/std/std_irq.h
index fb71ae09..4af55745 100644
--- a/import/chips/p9/procedures/ppe/pk/std/std_irq.h
+++ b/import/chips/p9/procedures/ppe/pk/std/std_irq.h
@@ -59,6 +59,14 @@ pk_irq_enable(PkIrqId irq)
     out64(STD_LCL_EIMR_CLR, STD_IRQ_MASK64(irq));
 }
 
+/// Enable a vector of interrupts by clearing the mask bits.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_enable(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EIMR_CLR, irq_vec_mask);
+}
 
 /// Disable an interrupt by setting the mask bit.
 
@@ -69,6 +77,15 @@ pk_irq_disable(PkIrqId irq)
     out64(STD_LCL_EIMR_OR, STD_IRQ_MASK64(irq));
 }
 
+/// Disable a vector of interrupts by setting the mask bits.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_disable(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EIMR_OR, irq_vec_mask);
+}
+
 
 /// Clear interrupt status with an CLR mask.  Only meaningful for
 /// edge-triggered interrupts.
@@ -81,6 +98,16 @@ pk_irq_status_clear(PkIrqId irq)
 }
 
 
+/// Clear a vector of interrupts status with an CLR mask.  Only meaningful for
+/// edge-triggered interrupts.
+
+UNLESS__PPE42_IRQ_CORE_C__(extern)
+inline void
+pk_irq_vec_status_clear(uint64_t irq_vec_mask)
+{
+    out64(STD_LCL_EISR_CLR, irq_vec_mask);
+}
+
 /// Get IRQ status as a 0 or non-0 integer
 
 UNLESS__PPE42_IRQ_CORE_C__(extern)