diff options
6 files changed, 154 insertions, 57 deletions
diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C index f39f216a..9cab5647 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -21,19 +21,19 @@ /// /// @brief Read scratch Regs, update ATTR //------------------------------------------------------------------------------ -// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> -// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> -// *HWP Team : Perv -// *HWP Level : 2 -// *HWP Consumed by : SBE +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ //## auto_generated #include "p9_sbe_attr_setup.H" -#include "p9_perv_scom_addresses.H" +#include <p9_perv_scom_addresses.H> fapi2::ReturnCode p9_sbe_attr_setup(const @@ -41,95 +41,158 @@ fapi2::ReturnCode p9_sbe_attr_setup(const { fapi2::buffer<uint64_t> l_read_scratch_reg = 0; fapi2::buffer<uint64_t> l_read_scratch8 = 0; - uint8_t l_read_1 = 0; - uint8_t l_read_2 = 0; - uint32_t l_read_3 = 0; - uint32_t l_read_4 = 0; - uint32_t l_read_5 = 0; - FAPI_DBG("Entering ..."); - - FAPI_INF("Read Scratch8 for validity of Scratch register"); + fapi2::buffer<uint8_t> l_read_1 = 0; + fapi2::buffer<uint8_t> l_read_2 = 0; + fapi2::buffer<uint8_t> l_read_3 = 0; + fapi2::buffer<uint16_t> l_read_4 = 0; + fapi2::buffer<uint32_t> l_read_5 = 0; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; + fapi2::buffer<uint64_t> l_data64; + FAPI_INF("Entering ..."); + + FAPI_DBG("Read Scratch8 for validity of Scratch register"); //Getting SCRATCH_REGISTER_8 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_8_SCOM, l_read_scratch8)); //l_read_scratch8 = PIB.SCRATCH_REGISTER_8 + //set_security_acess + { + fapi2::buffer<uint64_t> l_read_reg; + + FAPI_DBG("Reading ATTR_SECURITY_MODE"); + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SECURITY_MODE, FAPI_SYSTEM, l_read_1)); + + if ( l_read_1.getBit<7>() == 0 ) + { + FAPI_DBG("Clear Security Access Bit"); + //Setting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + l_data64.clearBit<4>(); //PIB.CBS_CS.CBS_CS_SECURE_ACCESS_BIT = 0 + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_CBS_CS_SCOM, l_data64)); + } + + //Getting CBS_CS register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_CBS_CS_SCOM, + l_read_reg)); //l_read_reg = PIB.CBS_CS + + l_read_1 = 0; + l_read_1.writeBit<7>(l_read_reg.getBit<4>()); + + FAPI_DBG("Setting ATTR_SECURITY_ENABLE with the SAB state"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SECURITY_ENABLE, FAPI_SYSTEM, l_read_1)); + + } //read_scratch1_reg { if ( l_read_scratch8.getBit<0>() ) { + FAPI_DBG("Reading Scratch_reg1"); //Getting SCRATCH_REGISTER_1 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_1_SCOM, l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_1 - l_read_scratch_reg.extractToRight<0, 8>(l_read_1); - l_read_scratch_reg.extractToRight<8, 24>(l_read_4); + l_read_scratch_reg.extract<0, 6>(l_read_1); + l_read_scratch_reg.extract<8, 24>(l_read_5); + FAPI_DBG("Setting up ATTR_EQ_GARD, ATTR_EC_GARD"); FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EQ_GARD, i_target_chip, l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_4)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_EC_GARD, i_target_chip, l_read_5)); + + l_read_1 = 0; + l_read_4 = 0; } } //read_scratch2_reg { if ( l_read_scratch8.getBit<1>() ) { + FAPI_DBG("Reading Scratch_reg2"); //Getting SCRATCH_REGISTER_2 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_2_SCOM, l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_2 - l_read_scratch_reg.extractToRight<0, 16>(l_read_3); + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_3)); + FAPI_DBG("Setting up ATTR_I2C_BUS_DIV_REF"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_I2C_BUS_DIV_REF, i_target_chip, l_read_4)); } } - //read_scratch3_reg - { - if ( l_read_scratch8.getBit<2>() ) - { - //Getting SCRATCH_REGISTER_3 register value - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_3_SCOM, - l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_3 - l_read_scratch_reg.extractToRight<0, 26>(l_read_4); - l_read_scratch_reg.extractToRight<26, 3>(l_read_1); - l_read_scratch_reg.extractToRight<29, 3>(l_read_2); - - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FLAGS, i_target_chip, l_read_4)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NODE_POS, i_target_chip, l_read_1)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_CHIP_POS, i_target_chip, l_read_2)); - } - } //read_scratch4_reg { if ( l_read_scratch8.getBit<3>() ) { + FAPI_DBG("Reading Scratch_Reg4"); //Getting SCRATCH_REGISTER_4 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_4_SCOM, l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_4 - l_read_scratch_reg.extractToRight<0, 16>(l_read_3); + l_read_scratch_reg.extractToRight<0, 16>(l_read_4); l_read_scratch_reg.extractToRight<24, 8>(l_read_1); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ, i_target_chip, l_read_3)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, i_target_chip, l_read_1)); + FAPI_DBG("Setting up ATTR_BOOT_FREQ_MULT, ATTR_NEST_PLL_BUCKET"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_BOOT_FREQ_MULT, i_target_chip, l_read_4)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_NEST_PLL_BUCKET, FAPI_SYSTEM, l_read_1)); + + l_read_1 = 0; + l_read_4 = 0; } } //read_scratch5_reg { if ( l_read_scratch8.getBit<4>() ) { + FAPI_DBG("Reading Scratch_reg5"); //Getting SCRATCH_REGISTER_5 register value FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_5_SCOM, l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_5 - l_read_scratch_reg.extractToRight<0, 16>(l_read_3); - l_read_scratch_reg.extractToRight<16, 16>(l_read_5); + l_read_1.writeBit<7>(l_read_scratch_reg.getBit<0>()); + l_read_2.writeBit<7>(l_read_scratch_reg.getBit<1>()); + l_read_3.writeBit<7>(l_read_scratch_reg.getBit<2>()); + + FAPI_DBG("Setting up SYSTEM_IPL_PHASE, RISK_LEVEL, SYS_FORCE_ALL_CORES"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYSTEM_IPL_PHASE, FAPI_SYSTEM, l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_SYS_FORCE_ALL_CORES, FAPI_SYSTEM, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_RISK_LEVEL, FAPI_SYSTEM, l_read_3)); + + l_read_1 = 0; + l_read_2 = 0; + l_read_3 = 0; - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VCS_BOOT_VOLTAGE, i_target_chip, l_read_3)); - FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_VDD_BOOT_VOLTAGE, i_target_chip, l_read_5)); + l_read_1.writeBit<7>(l_read_scratch_reg.getBit<3>()); + + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_DISABLE_HBBL_VECTORS, FAPI_SYSTEM, + l_read_1)); + + l_read_1 = 0; + } + } + //read_scratch6_reg + { + if ( l_read_scratch8.getBit<5>() ) + { + FAPI_DBG("Reading Scratch_reg6"); + //Getting SCRATCH_REGISTER_6 register value + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SCRATCH_REGISTER_6_SCOM, + l_read_scratch_reg)); //l_read_scratch_reg = PIB.SCRATCH_REGISTER_6 + + l_read_1.writeBit<7>(l_read_scratch_reg.getBit<24>()); + l_read_scratch_reg.extractToRight<26, 3>(l_read_2); + l_read_scratch_reg.extractToRight<29, 3>(l_read_3); + + FAPI_DBG("Settuing up MASTER_CHIP, FABRIC_GROUP_ID and CHIP_ID"); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_SBE_MASTER_CHIP, i_target_chip, + l_read_1)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_GROUP_ID, i_target_chip, + l_read_2)); + FAPI_TRY(FAPI_ATTR_SET(fapi2::ATTR_PROC_FABRIC_CHIP_ID, i_target_chip, + l_read_3)); } } - FAPI_DBG("Exiting ..."); + FAPI_INF("Exiting ..."); fapi_try_exit: return fapi2::current_err; diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H b/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H index 00200a86..60792470 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_attr_setup.H @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -21,12 +21,12 @@ /// /// @brief Read scratch Regs, update ATTR //------------------------------------------------------------------------------ -// *HWP HW Owner : Abhishek Agarwal <abagarw8@in.ibm.com> +// *HWP HW Owner : Anusha Reddy Rangareddygari <anusrang@in.ibm.com> // *HWP HW Backup Owner : Srinivas V Naga <srinivan@in.ibm.com> -// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> -// *HWP Team : Perv -// *HWP Level : 2 -// *HWP Consumed by : SBE +// *HWP FW Owner : sunil kumar <skumar8j@in.ibm.com> +// *HWP Team : Perv +// *HWP Level : 2 +// *HWP Consumed by : SBE //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C b/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C index a1be79be..1dcfd9ae 100644 --- a/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C +++ b/import/chips/p9/procedures/hwp/perv/p9_sbe_select_ex.C @@ -107,6 +107,7 @@ fapi2::ReturnCode p9_sbe_select_ex( uint8_t attr_force_all = 0; bool b_single = true; bool b_first = true; + const fapi2::Target<fapi2::TARGET_TYPE_SYSTEM> FAPI_SYSTEM; auto l_perv_functional_vector = i_target.getChildren<fapi2::TARGET_TYPE_PERV> @@ -170,7 +171,7 @@ fapi2::ReturnCode p9_sbe_select_ex( // Read the "FORCE_ALL" attribute FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_SYS_FORCE_ALL_CORES, - i_target, + FAPI_SYSTEM, attr_force_all)); // Set the flow mode and respect the force mode diff --git a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index a42b5294..d7b99d67 100644 --- a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -324,6 +324,7 @@ </description> <valueType>uint8</valueType> <platInit/> + <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> @@ -334,6 +335,7 @@ </description> <valueType>uint8</valueType> <platInit/> + <writeable/> </attribute> <!-- ********************************************************************** --> <attribute> diff --git a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml index 6e4fdd51..ee6491a4 100644 --- a/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/p9_sbe_attributes.xml @@ -576,4 +576,12 @@ <entry> <name>ATTR_SDISN_SETUP</name> </entry> + <entry> + <name>ATTR_SECURITY_MODE</name> + <value>0x0</value> + </entry> + <entry> + <name>ATTR_SECURITY_ENABLE</name> + </entry> + </entries> diff --git a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml index 0cb421d7..17f0564e 100644 --- a/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/pervasive_attributes.xml @@ -42,7 +42,7 @@ <id>ATTR_I2C_BUS_DIV_REF</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description>Ref clock I2C bus divider consumed by code running out of OTPROM</description> - <valueType>uint32</valueType> + <valueType>uint16</valueType> <persistRuntime/> <platInit/> <writeable/> @@ -165,7 +165,7 @@ <attribute> <id>ATTR_NEST_PLL_BUCKET</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Select Nest I2C and pll setting from one of the supported frequencies</description> <valueType>uint8</valueType> <persistRuntime/> @@ -196,24 +196,26 @@ <attribute> <id>ATTR_RISK_LEVEL</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description>HWP/Init "risk level" enabled. Used by HB to pass to HB driven HWPs</description> <valueType>uint8</valueType> <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> + <writeable/> </attribute> <attribute> <id>ATTR_DISABLE_HBBL_VECTORS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description>BootLoader HWP flag to not place 12K exception vectors. This flag is only applicable when security is disabled.</description> <valueType>uint8</valueType> <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> + <writeable/> </attribute> <attribute> @@ -290,7 +292,7 @@ <attribute> <id>ATTR_BOOT_FLAGS</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Switch to using a flag to indicate SEEPROM side SBE</description> <valueType>uint32</valueType> <persistRuntime/> @@ -437,6 +439,7 @@ <enum>FALSE = 0x0,TRUE = 0x1</enum> <persistRuntime/> <platInit/> + <writeable/> </attribute> <attribute> @@ -509,13 +512,14 @@ <attribute> <id>ATTR_SYS_FORCE_ALL_CORES</id> - <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <targetType>TARGET_TYPE_SYSTEM</targetType> <description>Indicate that p9_sbe_select_ex should force selection to ALL good EX chiplets having good cores even if only a single EX chiplet mode is executed. </description> <valueType>uint8</valueType> <persistRuntime/> <platInit/> + <writeable/> </attribute> <attribute> @@ -549,4 +553,23 @@ <platInit/> </attribute> +<attribute> + <id>ATTR_SECURITY_ENABLE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>Holds the state of Security Access Bit (SAB)</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> +</attribute> + +<attribute> + <id>ATTR_SECURITY_MODE</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description>If SBE image has ATTR_SECURITY_MODE == 0b1, then leave SAB bit as is + Else ATTR_SECURITY_MODE == 0b0, then clear the SAB bit</description> + <valueType>uint8</valueType> + <platInit/> + <writeable/> +</attribute> + </attributes> |
