diff options
4 files changed, 177 insertions, 167 deletions
diff --git a/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H b/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H index 7ff34b86..7b220d97 100644 --- a/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H +++ b/import/chips/p9/common/include/p9_obus_scom_addresses_fixes.H @@ -45,9 +45,14 @@ static const uint64_t SH_UNT_OBUS_1 = 514; static const uint64_t SH_UNT_OBUS_2 = 515; -REG64( OBUS_1_LL3_IOOL_CONTROL, +REG64( OBUS_1_LL1_IOOL_CONTROL, RULL(0x0A01080B), SH_UNT_OBUS_1, SH_ACS_SCOM ); -REG64( OBUS_2_LL3_IOOL_CONTROL, +REG64( OBUS_1_LL1_LL1_LL1_PB_IOOL_FIR_REG, + RULL(0x0A010800), SH_UNT_OBUS_2, SH_ACS_SCOM ); + +REG64( OBUS_2_LL2_IOOL_CONTROL, RULL(0x0B01080B), SH_UNT_OBUS_2, SH_ACS_SCOM ); +REG64( OBUS_2_LL2_LL2_LL2_PB_IOOL_FIR_REG, + RULL(0x0B010800), SH_UNT_OBUS_2, SH_ACS_SCOM ); #endif diff --git a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C index 2cc47ad3..2c11fdab 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C +++ b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.C @@ -7,7 +7,7 @@ /* */ /* EKB Project */ /* */ -/* COPYRIGHT 2015 */ +/* COPYRIGHT 2015,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -34,7 +34,7 @@ // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest // *HWP Level: 2 -// *HWP Consumed by: SBE,HB +// *HWP Consumed by: SBE,HB,FSP // //------------------------------------------------------------------------------ diff --git a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H index 7425d97f..b94e3b17 100644 --- a/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H +++ b/import/chips/p9/procedures/hwp/nest/p9_fbc_utils.H @@ -29,7 +29,7 @@ // *HWP FW Owner: Thi Tran <thi@us.ibm.com> // *HWP Team: Nest // *HWP Level: 2 -// *HWP Consumed by: SBE,HB +// *HWP Consumed by: SBE,HB,FSP // #ifndef _P9_FBC_UTILS_H_ @@ -39,145 +39,11 @@ // Includes //------------------------------------------------------------------------------ #include <fapi2.H> -#include <p9_perv_scom_addresses.H> -#include <p9_perv_scom_addresses_fld.H> -#include <p9_misc_scom_addresses.H> -#include <p9_misc_scom_addresses_fld.H> -#include <p9_xbus_scom_addresses.H> -#include <p9_xbus_scom_addresses_fld.H> -#include <p9_obus_scom_addresses.H> - //------------------------------------------------------------------------------ // Constant definitions //------------------------------------------------------------------------------ -// link types -enum p9_fbc_link_t -{ - XBUS = 0, - ABUS = 1 -}; - -// link constants -const uint32_t P9_FBC_UTILS_MAX_X_LINKS = 7; -const uint32_t P9_FBC_UTILS_MAX_A_LINKS = 4; - -// link control structure (DLL/TL/iovalid/FIRs) -struct p9_fbc_link_ctl_t -{ - p9_fbc_link_t link_type; - uint8_t link_id; - uint64_t iovalid_or_addr; - uint64_t iovalid_clear_addr; - uint8_t iovalid_field_start_bit; - uint8_t ras_fir_field_bit; - uint64_t dll_control_addr; -}; - -const p9_fbc_link_ctl_t P9_FBC_LINK_CTL_ARR[P9_FBC_UTILS_MAX_X_LINKS + P9_FBC_UTILS_MAX_A_LINKS] = -{ - { - XBUS, - 0, - PERV_XB_CPLT_CONF1_OR, - PERV_XB_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X0_FIR_ERR, - XBUS_0_LL0_IOEL_CONTROL - }, - { - XBUS, - 1, - PERV_XB_CPLT_CONF1_OR, - PERV_XB_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_6D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X1_FIR_ERR, - XBUS_1_LL1_IOEL_CONTROL - }, - { - XBUS, - 2, - PERV_XB_CPLT_CONF1_OR, - PERV_XB_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_8D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X2_FIR_ERR, - XBUS_2_LL2_IOEL_CONTROL - }, - { - XBUS, - 3, - PERV_OB0_CPLT_CONF1_OR, - PERV_OB0_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR, - OBUS_0_LL0_IOOL_CONTROL - }, - { - XBUS, - 4, - PERV_OB1_CPLT_CONF1_OR, - PERV_OB1_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR, - OBUS_1_LL3_IOOL_CONTROL - }, - { - XBUS, - 5, - PERV_OB2_CPLT_CONF1_OR, - PERV_OB2_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR, - OBUS_2_LL3_IOOL_CONTROL - }, - { - XBUS, - 6, - PERV_OB3_CPLT_CONF1_OR, - PERV_OB3_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR, - OBUS_3_LL3_IOOL_CONTROL - }, - { - ABUS, - 0, - PERV_OB0_CPLT_CONF1_OR, - PERV_OB0_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X3_FIR_ERR, - OBUS_0_LL0_IOOL_CONTROL - }, - { - ABUS, - 1, - PERV_OB1_CPLT_CONF1_OR, - PERV_OB1_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X4_FIR_ERR, - OBUS_1_LL3_IOOL_CONTROL - }, - { - ABUS, - 2, - PERV_OB2_CPLT_CONF1_OR, - PERV_OB2_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X5_FIR_ERR, - OBUS_2_LL3_IOOL_CONTROL - }, - { - ABUS, - 3, - PERV_OB3_CPLT_CONF1_OR, - PERV_OB3_CPLT_CONF1_CLEAR, - PERV_1_CPLT_CONF1_IOVALID_4D, - PU_PB_CENT_SM1_EXTFIR_MASK_REG_PB_X6_FIR_ERR, - OBUS_3_LL3_IOOL_CONTROL - } -}; - // address range definitions const uint64_t P9_FBC_UTILS_FBC_MAX_ADDRESS = ((1ULL << 56) - 1ULL); const uint64_t P9_FBC_UTILS_CACHELINE_MASK = 0x7FULL; @@ -191,45 +57,42 @@ const uint64_t FABRIC_CACHELINE_SIZE = 0x80; // Function prototypes //------------------------------------------------------------------------------ -extern "C" { - /// /// @brief Read FBC/ADU registers to determine state of fabric init and stop /// control signals /// -/// @param[in] i_target Reference to processor chip target -/// @param[out] o_is_initialized State of fabric init signal -/// @param[out] o_is_running State of fabric pervasive stop control +/// @param[in] i_target Reference to processor chip target +/// @param[out] o_is_initialized State of fabric init signal +/// @param[out] o_is_running State of fabric pervasive stop control /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_fbc_utils_get_fbc_state( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - bool& o_is_initialized, - bool& o_is_running); +fapi2::ReturnCode p9_fbc_utils_get_fbc_state( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + bool& o_is_initialized, + bool& o_is_running); /// /// @brief Use ADU pMisc Mode register to clear fabric stop signal, overriding /// a stop condition caused by a checkstop /// -/// @param[in] i_target Reference to processor chip target +/// @param[in] i_target Reference to processor chip target /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); +fapi2::ReturnCode p9_fbc_utils_override_fbc_stop( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); /// /// @brief Return base address origin (non-mirrored/mirrored) for this chip /// -/// @param[in] i_target Reference to processor chip target -/// @param[out] o_base_address_nm Non-mirrored base address for this chip -/// @param[out] o_base_address_m Mirrored base address for this chip +/// @param[in] i_target Reference to processor chip target +/// @param[out] o_base_address_nm Non-mirrored base address for this chip +/// @param[out] o_base_address_m Mirrored base address for this chip /// @return fapi::ReturnCode, FAPI2_RC_SUCCESS if success, else error code. /// - fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( - const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, - uint64_t& o_base_address_nm, - uint64_t& o_base_address_m); +fapi2::ReturnCode p9_fbc_utils_get_chip_base_address( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target, + uint64_t& o_base_address_nm, + uint64_t& o_base_address_m); -} // extern "C" #endif // _P9_FBC_UTILS_H_ diff --git a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml index a8c7bf06..254bd84e 100644 --- a/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml +++ b/import/chips/p9/procedures/xml/attribute_info/nest_attributes.xml @@ -148,18 +148,54 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_CORE_FLOOR_RATIO</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP core floor/nest frequency ratio + </description> + <valueType>uint8</valueType> + <enum> + RATIO_8_8 = 0x0, + RATIO_7_8 = 0x1, + RATIO_6_8 = 0x2, + RATIO_5_8 = 0x3, + RATIO_4_8 = 0x4, + RATIO_2_8 = 0x5 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_CORE_CEILING_RATIO</id> + <targetType>TARGET_TYPE_SYSTEM</targetType> + <description> + Processor SMP core celing/nest frequency ratio + </description> + <valueType>uint8</valueType> + <enum> + RATIO_8_8 = 0x0, + RATIO_7_8 = 0x1, + RATIO_6_8 = 0x2, + RATIO_5_8 = 0x3, + RATIO_4_8 = 0x4, + RATIO_2_8 = 0x5 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_PUMP_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> Processor SMP Fabric broadcast scope configuration. - MODE1 = default = chip_is_node - MODE2 = chip_is_group + CHIP_IS_NODE = MODE1 = default + CHIP_IS_GROUP = MODE2 Provided by the MRW. </description> <valueType>uint8</valueType> <enum> - MODE1 = 0x01, - MODE2 = 0x02 + CHIP_IS_NODE = 0x01, + CHIP_IS_GROUP = 0x02 </enum> <platInit/> </attribute> @@ -192,7 +228,6 @@ Provided by the MRW. </description> <valueType>uint8</valueType> - <array>4</array> <enum> SMP = 0x0, CAPI = 0x1, @@ -219,6 +254,25 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_OPTICS_CONFIG_MODE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Per-link optics configuration + 0 = default = SMP + 1 = CAPI 2.0 + 2 = NV 2.0 + </description> + <valueType>uint8</valueType> + <enum> + SMP = 0x0, + CAPI = 0x1, + NV = 0x2 + </enum> + <array>4</array> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_CAPI_MODE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> @@ -293,7 +347,6 @@ FALSE = 0x0, TRUE = 0x1 </enum> - <platInit/> <writeable/> </attribute> <!-- ********************************************************************** --> @@ -308,7 +361,6 @@ FALSE = 0x0, TRUE = 0x1 </enum> - <platInit/> <writeable/> </attribute> <!-- ********************************************************************** --> @@ -358,6 +410,19 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_X_ATTACHED_LINK_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric X link on this chip, specifies the link ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>7</array> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_A_ATTACHED_CHIP_ID</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -371,6 +436,33 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_A_ATTACHED_LINK_ID</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + For each fabric A link on this chip, specifies the link ID of the chip at the + receiving end of the link. Should be considered valid only if corresponding + ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG index is true. + </description> + <valueType>uint8</valueType> + <array>4</array> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_X_AGGREGATE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if X links on this chip should be configured in aggregate mode. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_X_ADDR_DIS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -388,6 +480,38 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_X_LINK_DELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Average of local/remote end link delay counter values. + Used to designate coherent link in aggregate configurations. + Should be considered valid only if corresponding ATTR_PROC_FABRIC_X_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint32</valueType> + <array>7</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> + <id>ATTR_PROC_FABRIC_A_AGGREGATE</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Indicates if A links on this chip should be configured in aggregate mode. + </description> + <valueType>uint8</valueType> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_FABRIC_A_ADDR_DIS</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> @@ -405,6 +529,24 @@ </attribute> <!-- ********************************************************************** --> <attribute> + <id>ATTR_PROC_FABRIC_A_LINK_DELAY</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Average of local/remote end link delay counter values. + Used to designate coherent link in aggregate configurations. + Should be considered valid only if corresponding ATTR_PROC_FABRIC_A_ATTACHED_CHIP_CNFG + index is true. + </description> + <valueType>uint32</valueType> + <array>4</array> + <enum> + OFF = 0x0, + ON = 0x1 + </enum> + <writeable/> +</attribute> +<!-- ********************************************************************** --> +<attribute> <id>ATTR_PROC_EPS_GB_PERCENTAGE</id> <targetType>TARGET_TYPE_SYSTEM</targetType> <description> @@ -450,7 +592,7 @@ Counter tier is index. </description> <valueType>uint32</valueType> - <array>3</array> + <array>2</array> <writeable/> </attribute> <!-- ********************************************************************** --> |
