diff options
3 files changed, 38 insertions, 1 deletions
diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C index c7533c6a..832b0c57 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.C @@ -221,6 +221,10 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const fapi2::ENUM_ATTR_SYSTEM_IPL_PHASE_CACHE_CONTAINED) //Skip for cache contained. { #endif + uint8_t l_is_p9c; + FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_EC_FEATURE_P9C_LOGIC_ONLY, + i_target_chip, + l_is_p9c)); // NEST OBUS XBUS PCI MC - Functional for (auto& targ : l_perv_func_WO_Core_Cache) @@ -481,6 +485,20 @@ fapi2::ReturnCode p9_sbe_chiplet_reset(const } } + for (auto& targ : l_perv_func) + { + //MC + uint32_t l_chipletID = targ.getChipletNumber(); + + if (l_is_p9c && (l_chipletID >= MC01_CHIPLET_ID && l_chipletID <= MC23_CHIPLET_ID)) + { + FAPI_DBG("Set TC_IOM_FASTX2_RATIO_DC"); + FAPI_TRY(fapi2::putScom(targ, + PERV_CPLT_CONF1_OR, + p9SbeChipletReset::MC_CPLT_CONF1_FASTX2_RATIO_MASK)); + } + } + #ifndef __PPE__ } diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H index f833f52b..519e98c3 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_chiplet_reset.H @@ -91,7 +91,8 @@ enum P9_SBE_CHIPLET_RESET_Public_Constants SIM_CYCLE_DELAY = 10000, // unit is cycles HANG_PULSE_0X12 = 0x12, HANG_PULSE_0X1C = 0x1C, - HANG_PULSE_0X08 = 0x08 + HANG_PULSE_0X08 = 0x08, + MC_CPLT_CONF1_FASTX2_RATIO_MASK = 0x0000C00000000000ULL }; } diff --git a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml index c44cf6a0..7565cb68 100644 --- a/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml +++ b/src/import/chips/p9/procedures/xml/attribute_info/chip_ec_attributes.xml @@ -4526,6 +4526,24 @@ <!-- ******************************************************************** --> <attribute> + <id>ATTR_CHIP_EC_FEATURE_HW418091</id> + <targetType>TARGET_TYPE_PROC_CHIP</targetType> + <description> + Adjust FRTL latency overflow check for HW418091 + </description> + <chipEcFeature> + <chip> + <name>ENUM_ATTR_NAME_CUMULUS</name> + <ec> + <value>0x10</value> + <test>EQUAL</test> + </ec> + </chip> + </chipEcFeature> + </attribute> + + <!-- ******************************************************************** --> + <attribute> <id>ATTR_CHIP_EC_FEATURE_HW355538</id> <targetType>TARGET_TYPE_PROC_CHIP</targetType> <description> |
