diff options
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C | 6 | ||||
| -rw-r--r-- | src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C | 6 |
2 files changed, 9 insertions, 3 deletions
diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C index 4b24e3d9..91b7d925 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -243,6 +243,12 @@ p9_hcd_cache_dpll_setup( FAPI_TRY(getScom(i_target, EQ_OPCG_ALIGN, l_data64)); l_data64.insertFromRight<47, 5>(0x3); FAPI_TRY(putScom(i_target, EQ_OPCG_ALIGN, l_data64)); + + FAPI_DBG("Clear PLL unlock errors in PCB slave, unmask FIR propagation"); + FAPI_TRY(putScom(i_target, EQ_ERROR_REG, 0xFFFFFFFFFFFFFFFF)); + FAPI_TRY(getScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64)); + l_data64.clearBit<12>(); + FAPI_TRY(putScom(i_target, EQ_SLAVE_CONFIG_REG, l_data64)); } FAPI_DBG("Drop skew/duty cycle adjust func_clksel via NET_CTRL0[22]"); diff --git a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C index beaf8d2a..e8d3f166 100644 --- a/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C +++ b/src/import/chips/p9/procedures/hwp/perv/p9_sbe_npll_setup.C @@ -268,12 +268,12 @@ fapi2::ReturnCode p9_sbe_npll_setup(const { FAPI_DBG(" Reset PCB error reg"); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_ERROR_REG, l_read_reg)); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_ERROR_REG, l_read_reg)); FAPI_DBG(" Unmasking pll unlock error in Pcb slave config reg"); - FAPI_TRY(fapi2::getScom(i_target_chip, PERV_SLAVE_CONFIG_REG, l_read_reg)); + FAPI_TRY(fapi2::getScom(i_target_chip, PERV_TP_SLAVE_CONFIG_REG, l_read_reg)); l_read_reg.clearBit<12>(); - FAPI_TRY(fapi2::putScom(i_target_chip, PERV_SLAVE_CONFIG_REG, l_read_reg)); + FAPI_TRY(fapi2::putScom(i_target_chip, PERV_TP_SLAVE_CONFIG_REG, l_read_reg)); } |
